公开(公告)号：US20190131425A1

公开(公告)日：2019-05-02

申请号：US15798273

申请日：2017-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh LU ,  Carlos H. DIAZ ,  Chih-Sheng CHANG ,  Cheng-Yi PENG ,  Ling-Yen YEH ,  Chien-Hsing LEE

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/94 ,  H01L21/28

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.

公开(公告)号：US20170207339A1

公开(公告)日：2017-07-20

申请号：US15478758

申请日：2017-04-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi PENG ,  Chih-Chieh YEH ,  Hung-Li CHIANG ,  Hung-Ming CHEN ,  Yee-Chia YEO

IPC: H01L29/78 ,  H01L23/31 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/322 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/322 ,  H01L21/324 ,  H01L21/823431 ,  H01L23/3171 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. An upper portion of the fin structure includes a first surface and a second surface which is inclined to the first surface. The semiconductor device structure also includes an isolation feature surrounding a lower portion of the fin structure. The semiconductor device structure further includes a passivation layer covering the first surface and the second surface of the upper portion. The passivation layer includes a semiconductor material and has a substantially uniform thickness. In addition, the semiconductor device structure includes an interfacial layer over the passivation layer. The interfacial layer includes the semiconductor material. The interfacial layer has a first portion covering the fin structure and a second portion covering the isolation feature. The passivation layer separates the fin structure from the interfacial layer.

公开(公告)号：US20160336319A1

公开(公告)日：2016-11-17

申请号：US14714229

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin YANG ,  Chia-Cheng HO ,  Chih Chieh YEH ,  Cheng-Yi PENG ,  Tsung-Lin LEE

IPC: H01L27/092 ,  H01L29/267 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate and forming a first gate structure over a first portion of the fin structure. A first nitride layer is formed over a second portion of the fin structure. The first nitride layer is exposed to ultraviolet radiation. Source/drain regions are formed at the second portion of the fin structure.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成翅片结构，并在翅片结构的第一部分上形成第一栅极结构。 在翅片结构的第二部分上形成第一氮化物层。 第一氮化物层暴露于紫外线辐射。 源极/漏极区域形成在鳍状结构的第二部分处。

公开(公告)号：US20230387302A1

公开(公告)日：2023-11-30

申请号：US18227712

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi PENG ,  Song-Bor LEE

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/0665 ,  H01L29/66636 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/41775 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/0673

Abstract: The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions. The semiconductor device further includes a gate-all-around (GAA) structure disposed between the first and second S/D regions and wrapped around each of the second nanostructured regions, a first inner spacer disposed between an epitaxial sub-region of the first S/D region and a gate sub-region of the GAA structure, a second inner spacer disposed between an epitaxial sub-region of the second S/D region and the gate sub-region of the GAA structure, and a passivation layer disposed on sidewalls of the first and second nanostructured regions

公开(公告)号：US20220149155A1

公开(公告)日：2022-05-12

申请号：US17582866

申请日：2022-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi PENG ,  Song-Bor LEE

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/092 ,  H01L29/10 ,  H01L29/04

Abstract: The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions, Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.

公开(公告)号：US20190326419A1

公开(公告)日：2019-10-24

申请号：US16459529

申请日：2019-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi PENG ,  Chih Chieh YEH ,  Chih-Sheng CHANG ,  Hung-Li CHIANG ,  Hung-Ming CHEN ,  Yee-Chia YEO

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

公开(公告)号：US20190064238A1

公开(公告)日：2019-02-28

申请号：US15683317

申请日：2017-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi PENG ,  Chia-Cheng HO ,  Ming-Shiang LIN ,  Chih-Sheng CHANG ,  Carlos H. DIAZ

IPC: G01R27/16

Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.

公开(公告)号：US20180102436A1

公开(公告)日：2018-04-12

申请号：US15837826

申请日：2017-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li CHIANG ,  Cheng-Yi PENG ,  Jyh-Cherng SHEU ,  Yee-Chia YEO

IPC: H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7849 ,  H01L21/26513 ,  H01L21/26586 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure, a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region, and a contact layer wrapping around the first strain material layer. A width of the source/drain region is smaller than a width of the channel region.

公开(公告)号：US20170317193A1

公开(公告)日：2017-11-02

申请号：US15653094

申请日：2017-07-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi PENG ,  Chih Chieh YEH ,  Chih-Sheng CHANG ,  Hung-Li CHIANG ,  Hung-Ming CHEN ,  Yee-Chia YEO

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/41725 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

公开(公告)号：US20170069756A1

公开(公告)日：2017-03-09

申请号：US15280216

申请日：2016-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li CHIANG ,  Cheng-Yi PENG ,  Jyh-Cherng SHEU ,  Yee-Chia YEO

IPC: H01L29/78 ,  H01L23/535 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7849 ,  H01L21/26513 ,  H01L21/26586 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure, a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region, and a contact layer wrapping around the first strain material layer. A width of the source/drain region is smaller than a width of the channel region.

Abstract translation: 半导体器件包括衬底，鳍状结构，设置在衬底上并且包括沟道区和源极/漏极区，栅极结构设置在鳍结构的至少一部分上，沟道区位于栅极结构之下， 源极/漏极区域在栅极结构外部，应变材料层设置在源极/漏极区域上，应变材料层向第一沟道区域提供应力，以及围绕第一应变材料层缠绕的接触层。 源极/漏极区域的宽度小于沟道区域的宽度。