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    FinFET Structures and Methods of Forming the Same
    21.
    发明申请
    FinFET Structures and Methods of Forming the Same 有权

    公开(公告)号：US20210043772A1

    公开(公告)日：2021-02-11

    申请号：US17077383

    申请日：2020-10-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Chung-Chiang Wu ,  Ching-Hwanq Su

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49

    Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

    Semiconductor device and manufacturing method thereof
    24.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US09508817B2

    公开(公告)日：2016-11-29

    申请号：US14454645

    申请日：2014-08-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yung-Sung Yen ,  Huan-Just Lin ,  Chun-Hsiung Lin ,  Chi-Cheng Hung

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

    CPC classification number: H01L29/42392 ,  H01L29/0676 ,  H01L29/78642 ,  H01L29/78696

    Abstract: A semiconductor structure, a semiconductor device, and a method for forming the semiconductor device are provided. In various embodiments, the method for forming the semiconductor device includes forming transistors on a substrate. Forming each transistor includes forming a doped region on the substrate. A nanowire is formed protruding from the doped region. An interlayer dielectric layer is deposited over the doped region. A dielectric layer is deposited over the interlayer dielectric layer and surrounding each of the nanowires. A first gate layer is deposited over the dielectric layer. The dielectric layer and first gate layer are etched to expose portions of the nanowires and the interlayer dielectric layer. A second gate layer is formed over the exposed interlayer dielectric layer and surrounding the first gate layer. Then, the second gate layer was patterned to remove the second gate layer on the interlayer dielectric layer between the transistors.

    Abstract translation: 提供半导体结构，半导体器件和用于形成半导体器件的方法。 在各种实施例中，用于形成半导体器件的方法包括在衬底上形成晶体管。 形成每个晶体管包括在衬底上形成掺杂区域。 形成从掺杂区域突出的纳米线。 在掺杂区域上沉积层间电介质层。 介电层沉积在层间电介质层上并围绕每个纳米线。 在电介质层上沉积第一栅极层。 蚀刻介电层和第一栅极层以暴露纳米线和层间介电层的部分。 第二栅极层形成在暴露的层间介电层上并围绕第一栅极层。 然后，对第二栅极层进行图案化以去除晶体管之间的层间电介质层上的第二栅极层。

    Directed Self-Assembly Process with Size-Restricted Guiding Patterns
    29.
    发明申请
    Directed Self-Assembly Process with Size-Restricted Guiding Patterns 审中-公开

    公开(公告)号：US20180350613A1

    公开(公告)日：2018-12-06

    申请号：US16041892

    申请日：2018-07-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Huei Weng ,  Kuan-Hsin Lo ,  Wei-Liang Lin ,  Chi-Cheng Hung

    IPC: H01L21/3065 ,  H01L21/306 ,  H01L21/033 ,  H01L21/027

    Abstract: A method includes providing a substrate; forming mandrel patterns over the substrate; and forming spacers on sidewalls of the mandrel patterns. The method further includes removing the mandrel patterns, thereby forming trenches that are at least partially surrounded by the spacers. The method further includes depositing a copolymer material in the trenches, wherein the copolymer material is directed self-assembling; and inducing microphase separation within the copolymer material, thereby defining a first constituent polymer surrounded by a second constituent polymer. The mandrel patterns have restricted sizes and a restricted configuration. The first constituent polymer includes cylinders arranged in a rectangular or square array.

    Directional patterning methods
    30.
    发明授权
    Directional patterning methods 有权

    公开(公告)号：US10049918B2

    公开(公告)日：2018-08-14

    申请号：US15395310

    申请日：2016-12-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Cheng Hung ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ta-Ching Yu ,  Yung-Sung Yen ,  Ziwei Fang ,  Tsai-Sheng Gau ,  Chin-Hsiang Lin ,  Kuei-Shun Chen

    IPC: H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L21/3115

    Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof. In some implementations, the directional patterning method disclosed herein can achieve oblique interconnects and/or slot (rectangular) via interconnects.

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