公开(公告)号：US20220310905A1

公开(公告)日：2022-09-29

申请号：US17839326

申请日：2022-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Hsiang TSENG ,  Chih-Lin WANG ,  Yi-Huang WU

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: A method for manufacturing a memory device is provided. The method includes etching an opening in a first dielectric layer; forming a bottom electrode, a resistance switching element, and a top electrode in the opening in the first dielectric layer; forming a second dielectric layer over the bottom electrode, the resistance switching element, and the top electrode; and forming an electrode via connected to a top surface of the top electrode in the second dielectric layer.

公开(公告)号：US20200075401A1

公开(公告)日：2020-03-05

申请号：US16678666

申请日：2019-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia HSIEH ,  Long-Jie HONG ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/485 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/02 ,  H01L29/45 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

公开(公告)号：US20180090561A1

公开(公告)日：2018-03-29

申请号：US15830979

申请日：2017-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US20170154954A1

公开(公告)日：2017-06-01

申请号：US14954524

申请日：2015-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US20170141205A1

公开(公告)日：2017-05-18

申请号：US14940832

申请日：2015-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ruei YEH ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/51 ,  H01L29/45 ,  H01L21/02 ,  H01L29/40 ,  H01L21/768 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/518 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a metal gate electrode structure over the semiconductor substrate. The semiconductor device structure includes an insulating layer over the semiconductor substrate and surrounding the metal gate electrode structure. The semiconductor device structure includes a first metal nitride layer over a first top surface of the metal gate electrode structure and in direct contact with the metal gate electrode structure. The first metal nitride layer includes a nitride material of the metal gate electrode structure.

公开(公告)号：US20160071799A1

公开(公告)日：2016-03-10

申请号：US14477689

申请日：2014-09-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia HSIEH ,  Long-Jie HONG ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L23/535 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L21/285 ,  H01L21/321 ,  H01L29/66 ,  H01L29/16 ,  H01L21/311

CPC classification number: H01L21/76831 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31105 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76855 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

Abstract translation: 半导体器件包括衬底，外延层，第一蚀刻停止层，层间电介质（ILD）层，第二蚀刻停止层，保护层，衬垫，硅化物帽和接触插塞。 基板具有第一部分和第二部分。 外延层设置在第一部分中。 第一蚀刻停止层设置在第二部分上。 ILD层设置在第一蚀刻停止层上。 第二蚀刻停止层设置在ILD层上，其中第一蚀刻停止层，ILD层和第二蚀刻停止层形成围绕第一部分的侧壁。 保护层设置在侧壁上。 衬垫设置在保护层上。 硅化物盖设置在外延层上。 接触插头设置在硅化物盖上并被衬垫包围。

公开(公告)号：US20210335662A1

公开(公告)日：2021-10-28

申请号：US17365911

申请日：2021-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia HSIEH ,  Long-Jie HONG ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L21/768 ,  H01L29/16 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L23/485 ,  H01L21/8238 ,  H01L29/165

Abstract: A device includes an isolation structure, a source/drain epi-layer, a contact, a first dielectric layer, and a second dielectric layer. The isolation structure is embedded in a substrate. The source/drain epi-layer is embedded in the substrate and is in contact with the isolation structure. The contact is over the source/drain epi-layer. The first dielectric layer wraps the contact. The second dielectric layer is between the contact and the first dielectric layer. The first and second dielectric layers include different materials, and a portion of the source/drain epi-layer is directly between a bottom portion of the second dielectric layer and a top portion of the isolation structure.

公开(公告)号：US20210082482A1

公开(公告)日：2021-03-18

申请号：US16572329

申请日：2019-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Zong-You LUO ,  Ya-Jui TSOU ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.

公开(公告)号：US20200312719A1

公开(公告)日：2020-10-01

申请号：US16901815

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Long-Jie HONG ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes an active area having source and drain regions and a channel region between the source and drain regions, an isolation structure surrounding the active area, and a gate structure over the channel region of the active area and over the isolation structure, wherein the isolation structure has a first portion under the gate structure and a second portion free from coverage by the gate structure, and a top of the first portion of the isolation structure is lower than a top of the second portion of the isolation structure.

公开(公告)号：US20200044016A1

公开(公告)日：2020-02-06

申请号：US16595100

申请日：2019-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.