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    SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR
    22.
    发明申请
    SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR 有权

    公开(公告)号：US20210343787A1

    公开(公告)日：2021-11-04

    申请号：US17078583

    申请日：2020-10-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ken-Ichi Goto ,  Chung-Te Lin ,  Mauricio Manfrini

    IPC: H01L27/22 ,  H01L27/24

    Abstract: The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and an interconnect structure disposed over the substrate. The interconnect structure comprises stacked interconnect metal layers disposed within stacked interlayer dielectric (ILD) layers. A memory cell is disposed between an upper interconnect metal layer and an intermediate interconnect metal layer. A selecting transistor is connected to the memory cell and disposed between the intermediate interconnect metal layer and a lower interconnect metal layer. By placing the selecting transistor within the back-end interconnect structure between two interconnect metal layers, front-end space is saved, and more integration flexibility is provided.

    MEMORY CELL WITH MAGNETIC ACCESS SELECTOR APPARATUS
    23.
    发明申请
    MEMORY CELL WITH MAGNETIC ACCESS SELECTOR APPARATUS 有权

    公开(公告)号：US20210296573A1

    公开(公告)日：2021-09-23

    申请号：US16824862

    申请日：2020-03-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mauricio Manfrini

    IPC: H01L43/08 ,  H01L43/02 ,  H01L27/22

    Abstract: An integrated chip has a memory cell that includes a magnetic tunnel junction (MTJ) device and an access selector apparatus. The MTJ device includes a free layer and a pinned layer. The access selector apparatus includes a first metal structure and a second metal structure separated by one or more non-metallic layers. The first metal structure includes a polarized magnetic layer. The polarized magnetic layer produces a magnetic field that extends through the free layer, tilting its magnetic field and thereby substantially reducing a switching time for the MTJ device. The access selector apparatus may be a bipolar selector. The polarized magnetic layer may be incorporated into an electrode of the bipolar selector. Both the access selector apparatus and the MTJ device may be formed by a stack of material layers. The resulting memory cell may be compact and have good write speed.

    HIGH-DENSITY 3D-DRAM CELL WITH SCALED CAPACITORS
    24.
    发明申请
    HIGH-DENSITY 3D-DRAM CELL WITH SCALED CAPACITORS 有权

    公开(公告)号：US20210242208A1

    公开(公告)日：2021-08-05

    申请号：US17086628

    申请日：2020-11-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mauricio Manfrini ,  Chung-Te Lin

    IPC: H01L27/108

    Abstract: A semiconductor device comprises a semiconductor substrate, and a pair of metal gates extends upwards from the semiconductor substrate. First and second channel regions are disposed between inner sidewalls of the pair of metal gates. First and second drain regions are disposed between the inner sidewalls of the pair of metal gates and are disposed directly over the first and second channel regions, respectively. First and second source regions are disposed between the inner sidewalls of the pair of metal gates directly below the first and second channel regions, respectively. A capacitor dielectric structure is disposed below the first and second source regions. A bottom capacitor electrode is disposed below the capacitor dielectric. The capacitor dielectric structure separates the first and second drain regions from the bottom capacitor electrode.

    Semiconductor device and method of fabricating the same
    28.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US11264498B2

    公开(公告)日：2022-03-01

    申请号：US16901004

    申请日：2020-06-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Gerben Doornbos ,  Blandine Duriez ,  Georgios Vellianitis ,  Marcus Johannes Henricus Van Dal ,  Mauricio Manfrini

    IPC: H01L29/78 ,  H01L29/66 ,  H01L27/11587 ,  H01L27/1159

    Abstract: A semiconductor device includes a semiconductor substrate, a first source region, a first drain region, a first gate, a second source region, a second drain region, a second gate, and a first dielectric layer. The first source region and the first drain region are disposed within the semiconductor substrate. The first gate is disposed over the semiconductor substrate in between the first source region and the first drain region. The second source region and the second drain region are disposed within the semiconductor substrate. The second gate is disposed over the semiconductor substrate in between the second source region and the second drain region. The first dielectric layer is located in between the first gate and the semiconductor substrate, and in between the second gate and the semiconductor substrate, wherein the first dielectric layer extends from a position below the first gate to a position below the second gate.

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