公开(公告)号：US20220020771A1

公开(公告)日：2022-01-20

申请号：US17018232

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Han-Jong Chia ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/768

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

公开(公告)号：US11195834B2

公开(公告)日：2021-12-07

申请号：US16866506

申请日：2020-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu

IPC: H01L29/76 ,  H01L27/092 ,  H01L27/11546 ,  H01L27/11526 ,  H01L27/11575 ,  H01L29/10 ,  H01L21/266 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US20210375927A1

公开(公告)日：2021-12-02

申请号：US17012848

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Chung-Te Lin ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11556

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

公开(公告)号：US11088040B2

公开(公告)日：2021-08-10

申请号：US16578303

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/423 ,  H01L27/11519

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

公开(公告)号：US10937879B2

公开(公告)日：2021-03-02

申请号：US16195680

申请日：2018-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Wei-Cheng Wu ,  Te-Hsin Chiu

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/792 ,  H01L21/02 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/1157

Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.

公开(公告)号：US10804093B2

公开(公告)日：2020-10-13

申请号：US16587819

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei ,  Meng-Han Lin

IPC: H01L21/02 ,  H01L23/00 ,  H01L29/735 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10

Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

公开(公告)号：US20200243552A1

公开(公告)日：2020-07-30

申请号：US16848921

申请日：2020-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Wei Cheng Wu ,  Chih-Pin Huang

IPC: H01L27/11548 ,  H01L21/321 ,  H01L21/762 ,  H01L27/11524 ,  H01L23/532 ,  H01L21/033 ,  H01L29/66 ,  H01L21/768 ,  H01L29/423

Abstract: Various embodiments of the present application are directed to a method of forming an integrated circuit (IC). An isolation structure is formed between a logic region and a memory region of a substrate. A dummy structure is formed on the isolation structure and defines a dummy sidewall of the dummy structure facing the logic region. A boundary sidewall spacer is formed covering the dummy structure and at least partially defines a boundary sidewall of the boundary sidewall spacer facing the logic region. A protecting dielectric layer is formed on a top surface of the boundary sidewall spacer by converting an uppermost portion of the boundary sidewall spacer to the protecting dielectric layer. The protecting dielectric layer is removed, and a logic device structure is formed on the logic region.

公开(公告)号：US20200083126A1

公开(公告)日：2020-03-12

申请号：US16682210

申请日：2019-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/423

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

公开(公告)号：US10510855B2

公开(公告)日：2019-12-17

申请号：US15989606

申请日：2018-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

Abstract: The present disclosure, in some embodiments, relates to a transistor device within an active area having a shape configured to reduce a susceptibility of the transistor device to performance degradation (e.g., the kink effect) caused by divots in an adjacent isolation structure. The transistor device has a substrate including interior surfaces defining a trench within an upper surface of the substrate. One or more dielectric materials are arranged within the trench. The one or more dielectric materials define an opening exposing the upper surface of the substrate. The opening has a source opening over a source region within the substrate, a drain opening over a drain region within the substrate, and a channel opening between the source opening and the drain opening. The source opening and the drain opening have widths smaller than the channel opening. A gate structure extends over the opening between the source and drain regions.

公开(公告)号：US10510685B2

公开(公告)日：2019-12-17

申请号：US15935363

申请日：2018-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei ,  Meng-Han Lin

IPC: H01L23/00 ,  H01L29/735 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10

Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.