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    PACKAGE STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    23.
    发明申请
    PACKAGE STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20200118960A1

    公开(公告)日：2020-04-16

    申请号：US16714824

    申请日：2019-12-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Chih Chen ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Po-Han Wang

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/075 ,  H01L25/07 ,  H01L25/11 ,  H01L25/04 ,  H01L23/538

    Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die has a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

    PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    26.
    发明申请
    PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20190237423A1

    公开(公告)日：2019-08-01

    申请号：US15884254

    申请日：2018-01-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Chih Chen ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao

    IPC: H01L23/00 ,  H01L23/29

    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, an encapsulant, a first RDL structure, and a conductive terminal. The encapsulant is aside the first die, encapsulating sidewalls of the first die. The first RDL structure is on the first die and the encapsulant. The conductive terminal is electrically connected to first die through the RDL structure. The first RDL structure comprises a first polymer layer and a first RDL, the first polymer layer comprises a non-shrinkage material and a top surface of the first polymer layer is substantially flat.

    STACKED VIA STRUCTURE AND METHOD OF FABRICATING THE SAME
    27.
    发明申请
    STACKED VIA STRUCTURE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20190131235A1

    公开(公告)日：2019-05-02

    申请号：US15879457

    申请日：2018-01-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

    IPC: H01L23/522 ,  H01L21/66 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L21/768 ,  H01L23/00

    Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

    Semiconductor device and method of manufacturing the same
    29.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US10204870B2

    公开(公告)日：2019-02-12

    申请号：US15289173

    申请日：2016-10-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Zi-Jheng Liu ,  Jo-Lin Lan ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

    IPC: H01L23/544 ,  H01L23/538 ,  H01L23/00 ,  H01L23/58 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56

    Abstract: A method of manufacturing a semiconductor device includes: receiving a semiconductor structure having a chip region, a seal ring region surrounding the chip region, and a scribe region surroundingly defined around the seal ring region, the semiconductor structure including: a semiconductor chip in the chip region; and a molding compound disposed around the semiconductor chip and distributed in the chip region, the seal ring region and the scribe region; forming an insulating film over the chip region of the semiconductor structure and the seal ring region of the semiconductor structure; forming a seal ring over the seal ring region of the semiconductor structure and laterally adjacent to the insulating film, in which the seal ring has an exposed lateral surface facing away from the insulating film; and forming a protective layer that defines a substantially smooth and inclined lateral surface over the exposed lateral surface of the seal ring.

    INTEGRATED CIRCUIT PACKAGE AND METHOD OF FABRICATING THE SAME
    30.
    发明申请
    INTEGRATED CIRCUIT PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20180301389A1

    公开(公告)日：2018-10-18

    申请号：US15486306

    申请日：2017-04-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Zi-Jheng Liu ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

    IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/11 ,  H01L23/544 ,  H01L21/56 ,  H01L25/00 ,  H01L21/321 ,  H01L21/683

    Abstract: An integrated circuit package including an integrated circuit component, a patterned dielectric liner, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component includes an active surface and conductive vias distributed on the active surface. The patterned dielectric liner conformally covers the active surface of the integrated circuit component and sidewalls of the conductive vias. The insulating encapsulation encapsulates sidewalls of the integrated circuit component and covers the patterned dielectric liner. The insulating encapsulation includes a planar top surface. The planar top surface of the insulating encapsulation is substantially coplanar with top surfaces of the conductive vias. The insulating encapsulation and the conductive vias are spaced apart by the patterned dielectric liner. The redistribution circuit structure is disposed on the planar top surface of the insulating encapsulation, the top surfaces of the conductive vias and the patterned dielectric liner. The redistribution circuit structure is electrically connected to the conductive vias.

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