公开(公告)号：US20210125858A1

公开(公告)日：2021-04-29

申请号：US16823943

申请日：2020-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Meng-Yu LIN ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC: H01L21/768 ,  H01L21/02

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

公开(公告)号：US20200098923A1

公开(公告)日：2020-03-26

申请号：US16696845

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

公开(公告)号：US20180175213A1

公开(公告)日：2018-06-21

申请号：US15615498

申请日：2017-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Chung-Cheng WU ,  Carlos H. DIAZ ,  Chih-Hao WANG ,  Ken-Ichi GOTO ,  Ta-Pen GUO ,  Yee-Chia YEO ,  Zhiqiang WU ,  Yu-Ming LIN

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/16 ,  H01L29/24 ,  H01L21/02 ,  H01L21/8256

CPC classification number: H01L29/78696 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/823821 ,  H01L21/8256 ,  H01L27/0886 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/7851

Abstract: Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.