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公开(公告)号：US12278208B2
公开(公告)日：2025-04-15
申请号：US18499242
申请日：2023-11-01
Inventor： Mao-Yen Chang , Chih-Wei Lin , Hao-Yi Tsai , Kuo-Lung Pan , Chun-Cheng Lin , Tin-Hao Kuo , Yu-Chia Lai , Chih-Hsuan Tai
IPC: H01L21/56 , H01L23/00 , H01L23/538 , H01L25/00 , H01L25/18
Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.
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公开(公告)号：US20240371814A1
公开(公告)日：2024-11-07
申请号：US18776271
申请日：2024-07-18
Inventor： Yu-Chia Lai , Chih-Horng Chang , Hao-Yi Tsai , Chih-Hsuan Tai
IPC: H01L23/00 , H01L21/56 , H01L21/683 , H01L23/31 , H01L25/10
Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a redistribution circuit structure. The semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure includes conductive patterns, wherein the conductive patterns each comprise a first portion, at least one second portion, and at least one connecting portion. A first edge of the at least one connecting portion is connected to the first portion, and a second edge of the at least one connecting portion is connected to the at least one second portion, wherein the first edge is opposite to the second edge, and a length of the first edge is greater than a length of the second edge.
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公开(公告)号：US20240088307A1
公开(公告)日：2024-03-14
申请号：US18513644
申请日：2023-11-20
Inventor： Chih-Hsuan Tai , Hao-Yi Tsai , Yu-Chih Huang , Chih-Hao Chang , Chia-Hung Liu , Ban-Li Wu , Ying-Cheng Tseng , Po-Chun Lin
IPC: H01L31/0203 , H01L31/02 , H01L31/024 , H01L31/18
CPC classification number: H01L31/0203 , H01L31/02002 , H01L31/024 , H01L31/1892
Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure. A method of forming the semiconductor package is also provided.
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公开(公告)号：US11749582B2
公开(公告)日：2023-09-05
申请号：US17874293
申请日：2022-07-27
Inventor： Yu-Chia Lai , Chen-Hua Yu , Chung-Shi Liu , Hsiao-Chung Liang , Hao-Yi Tsai , Chien-Ling Hwang , Kuo-Lung Pan , Pei-Hsuan Lee , Tin-Hao Kuo , Chih-Hsuan Tai
CPC classification number: H01L23/4006 , H01L23/58 , H01L24/16 , H01L25/18 , H01L2023/405 , H01L2023/4068 , H01L2023/4087 , H01L2224/023 , H01L2224/16145
Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.
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公开(公告)号：US11580767B2
公开(公告)日：2023-02-14
申请号：US17017640
申请日：2020-09-10
Inventor： Chih-Hsuan Tai , Chih-Hua Chen , Hao-Yi Tsai , Yu-Chih Huang , Chia-Hung Liu , Ting-Ting Kuo , Ying-Cheng Tseng
Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.
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Patent Agency Ranking
公开(公告)号：US20220359343A1
公开(公告)日：2022-11-10
申请号：US17874293
申请日：2022-07-27
Inventor： Yu-Chia Lai , Chen-Hua Yu , Chung-Shi Liu , Hsiao-Chung Liang , Hao-Yi Tsai , Chien-Ling Hwang , Kuo-Lung Pan , Pei-Hsuan Lee , Tin-Hao Kuo , Chih-Hsuan Tai
Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.
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公开(公告)号：US20220285566A1
公开(公告)日：2022-09-08
申请号：US17750419
申请日：2022-05-23
Inventor： Chih-Hsuan Tai , Hao-Yi Tsai , Yu-Chih Huang , Chih-Hao Chang , Chia-Hung Liu , Ban-Li Wu , Ying-Cheng Tseng , Po-Chun Lin
IPC: H01L31/0203 , H01L31/18 , H01L31/024 , H01L31/02
Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure. A method of forming the semiconductor package is also provided.
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公开(公告)号：US11049850B2
公开(公告)日：2021-06-29
申请号：US16876471
申请日：2020-05-18
Inventor： Chih-Hsuan Tai , Chi-Hui Lai , Ying-Cheng Tseng , Ban-Li Wu , Ting-Ting Kuo , Yu-Chih Huang , Chiahung Liu , Hao-Yi Tsai , Chung-Shi Liu , Chen-Hua Yu
Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
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公开(公告)号：US20200279837A1
公开(公告)日：2020-09-03
申请号：US16876471
申请日：2020-05-18
Inventor： Chih-Hsuan Tai , Chi-Hui Lai , Ying-Cheng Tseng , Ban-Li Wu , Ting-Ting Kuo , Yu-Chih Huang , Chiahung Liu , Hao-Yi Tsai , Chung-Shi Liu , Chen-Hua Yu
Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
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公开(公告)号：US20190131287A1
公开(公告)日：2019-05-02
申请号：US16129479
申请日：2018-09-12
Inventor： Yu-Chih Huang , Chi-Hui Lai , Ban-Li Wu , Ying-Cheng Tseng , Ting-Ting Kuo , Chih-Hsuan Tai , Hao-Yi Tsai , Chuei-Tang Wang , Chung-Shi Liu , Chen-Hua Yu , Chiahung Liu
IPC: H01L25/16 , H01L23/498 , H01L21/48 , H01L21/50
Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.
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