公开(公告)号：US20240321786A1

公开(公告)日：2024-09-26

申请号：US18735151

申请日：2024-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Hao Tsai ,  Tzu-Chun Tang ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC分类号： H01L23/66 ,  H01L23/00 ,  H01L23/29

CPC分类号： H01L23/66 ,  H01L23/291 ,  H01L24/19 ,  H01L24/25 ,  H01L24/29 ,  H01L2223/6677 ,  H01L2224/19 ,  H01L2224/25171 ,  H01L2224/255 ,  H01L2224/29024 ,  H01L2224/32146

摘要： A manufacturing method of a package structure includes: providing a carrier substrate with an integrated circuit (IC) die, where the IC die is disposed in a cavity of the carrier substrate, and a thermally conductive layer is formed in the cavity to separate the IC die from the carrier substrate; forming a redistribution structure on a first side of the carrier substrate, where the redistribution structure is electrically coupled to the IC die; forming an antenna pattern over the redistribution structure; forming a patterned dielectric layer with an opening on a second side of the carrier substrate opposite to the first side, where a portion of the second side of the carrier substrate is exposed by the opening; and forming an underfill to be in thermal contact with the carrier substrate, where the underfill extends outward beyond an edge of the carrier substrate.

公开(公告)号：US12094860B2

公开(公告)日：2024-09-17

申请号：US18162671

申请日：2023-01-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Tzu-Chun Tang

IPC分类号： H01L23/552 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/66 ,  H01L25/16 ,  H01Q9/04 ,  H01Q9/16 ,  H01Q21/06 ,  H01Q21/08

CPC分类号： H01L25/16 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/552 ,  H01L23/66 ,  H01L24/19 ,  H01L24/24 ,  H01Q9/0407 ,  H01Q9/16 ,  H01L2223/6677 ,  H01L2224/24265 ,  H01Q21/061 ,  H01Q21/08

摘要： A package structure includes a semiconductor die, an antenna substrate structure, a redistribution layer. The semiconductor die laterally encapsulated by a first encapsulant. The antenna substrate structure disposed over the semiconductor die, wherein the antenna substrate structure includes a first type of antenna, and a second type of antenna disposed on a side of the antenna substrate structure facing away from the semiconductor die. The redistribution layer disposed between the semiconductor die and the antenna substrate structure. The semiconductor die, the first type of antenna, and the second type of antenna are electrically coupled through the redistribution layer. The polarization of radiation emitted by the first type of antenna is perpendicular to a polarization of radiation emitted by the second type of antenna.

公开(公告)号：US20240258287A1

公开(公告)日：2024-08-01

申请号：US18633459

申请日：2024-04-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Tzu-Chun Tang

IPC分类号： H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/552 ,  H01L23/66 ,  H01Q9/04 ,  H01Q9/16 ,  H01Q21/06 ,  H01Q21/08

CPC分类号： H01L25/16 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/552 ,  H01L23/66 ,  H01L24/19 ,  H01L24/24 ,  H01Q9/0407 ,  H01Q9/16 ,  H01L2223/6677 ,  H01L2224/24265 ,  H01Q21/061 ,  H01Q21/08

摘要： A package structure includes a semiconductor die, an antenna substrate structure, a redistribution layer. The semiconductor die laterally encapsulated by a first encapsulant. The antenna substrate structure disposed over the semiconductor die, wherein the antenna substrate structure includes a first type of antenna, and a second type of antenna disposed on a side of the antenna substrate structure facing away from the semiconductor die. The redistribution layer disposed between the semiconductor die and the antenna substrate structure. The semiconductor die, the first type of antenna, and the second type of antenna are electrically coupled through the redistribution layer. The polarization of radiation emitted by the first type of antenna is perpendicular to a polarization of radiation emitted by the second type of antenna.

公开(公告)号：US12040281B2

公开(公告)日：2024-07-16

申请号：US17401330

申请日：2021-08-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chuei-Tang Wang ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Yuan Chang ,  Jiun-Yi Wu ,  Jeng-Shien Hsieh ,  Tin-Hao Kuo

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/5385 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/24226 ,  H01L2224/82005 ,  H01L2924/3511

摘要： A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.

公开(公告)号：US12033963B2

公开(公告)日：2024-07-09

申请号：US17461957

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Hao Tsai ,  Tzu-Chun Tang ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC分类号： H01L23/66 ,  H01L23/00 ,  H01L23/29

CPC分类号： H01L23/66 ,  H01L23/291 ,  H01L24/19 ,  H01L24/25 ,  H01L24/29 ,  H01L2223/6677 ,  H01L2224/19 ,  H01L2224/25171 ,  H01L2224/255 ,  H01L2224/29024 ,  H01L2224/32146

摘要： A package structure and a manufacturing method thereof are provided. The package structure includes a carrier substrate, an integrated circuit (IC) die thermally coupled to the carrier substrate through a thermally conductive layer, an antenna pattern disposed over the carrier substrate and the IC die, a redistribution structure disposed between the antenna pattern and the IC die, and an underfill disposed below and thermally coupled to the carrier substrate. The antenna pattern is electrically coupled to the IC die.

公开(公告)号：US20240170386A1

公开(公告)日：2024-05-23

申请号：US18420775

申请日：2024-01-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chuei-Tang Wang ,  Chun-Lin Lu ,  Kai-Chiang Wu

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/66 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/16

CPC分类号： H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/16 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/3511

摘要： A package structure includes a conductive feature structure, a die, an adhesive layer, an insulator, a through via, and an encapsulant. The die is disposed over the conductive feature structure. The adhesive layer is disposed below the die. The insulator is disposed between the adhesive layer and a polymer layer of the conductive feature structure. The through via extends through the insulator to connect to the conductive feature structure. The encapsulant is disposed on the insulator and the conductive feature structure, laterally encapsulating the die and the through via, and between the through via and the insulator. The insulator has a coefficient of thermal expansion less than a coefficient of thermal expansion of the encapsulant.

公开(公告)号：US20240061195A1

公开(公告)日：2024-02-22

申请号：US18497999

申请日：2023-10-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chieh Chang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC分类号： G02B6/42 ,  H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC分类号： G02B6/4274 ,  H01L25/167 ,  H01L24/20 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  G02B6/4239 ,  G02B6/4202 ,  H01L23/5389 ,  H01L2224/214

摘要： A package assembly and a manufacturing method thereof are provided. The package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.

公开(公告)号：US20230260920A1

公开(公告)日：2023-08-17

申请号：US18303595

申请日：2023-04-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chuei-Tang Wang ,  Chen-Hua Yu

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

CPC分类号： H01L23/5389 ,  H01L23/5386 ,  H01L23/3114 ,  H01L24/20 ,  H01L25/0652 ,  H01L21/4857 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/6835 ,  H01L24/19 ,  H01L25/50 ,  H01L23/5383 ,  H01L25/0657 ,  H01L23/3121 ,  H01L21/568 ,  H01L2224/214 ,  H01L2221/68372 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L24/73 ,  H01L24/32 ,  H01L2224/18 ,  H01L2924/181 ,  H01L2224/2919 ,  H01L2924/00014 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/48227 ,  H01L2225/06527 ,  H01L24/29 ,  H01L24/48 ,  H01L24/83 ,  H01L2924/15311 ,  H01L2224/83191

摘要： A chip package includes a redistribution layer, at least one first semiconductor chip, an integrated fan-out package, and an insulating encapsulation. The at least one first semiconductor chip and the integrated fan-out package are electrically connected to the redistribution layer, wherein the at least one first semiconductor chip and the integrated fan-out package are located on a surface of the redistribution layer and electrically communicated to each other through the redistribution layer, and wherein the integrated fan-out package includes at least one second semiconductor chip. The insulating encapsulation encapsulates the at least one first semiconductor chip and the integrated fan-out package.

公开(公告)号：US11646313B2

公开(公告)日：2023-05-09

申请号：US17357803

申请日：2021-06-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chang-Fen Hu ,  Shao-Yu Li ,  Kuo-Ji Chen ,  Chih-Peng Lin ,  Chuei-Tang Wang ,  Ching-Fang Chen

IPC分类号： H01L27/092 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L27/092 ,  H01L23/5383 ,  H01L25/0655 ,  H01L25/50 ,  H01L25/0657

摘要： A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a PMOS transistor and an NMOS transistor. A first source/drain region of the PMOS transistor may be connected to a first source/drain region of the NMOS transistor and the die-to-die interconnect.

公开(公告)号：US20220384337A1

公开(公告)日：2022-12-01

申请号：US17884548

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chuei-Tang Wang ,  Tin-Hao Kuo

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498

摘要： A package structure including an interposer, a semiconductor die, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The interposer includes a core structure having a first and second surface, first metal layers disposed on the first and second surface, second metal layers disposed on the second surface over the first metal layers, and third metal layers disposed on the second surface over the second metal layers. The semiconductor die is disposed on the interposer. The through insulator vias are disposed on the interposer and electrically connected to the plurality of first metal layers. The insulating encapsulant is disposed on the interposer over the first surface and encapsulating the semiconductor die and the plurality of through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the semiconductor die and the plurality of through insulator vias.