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公开(公告)号：US20240355691A1
公开(公告)日：2024-10-24
申请号：US18761238
申请日：2024-07-01
Inventor： Chun-Cheng Lin , Ching-Hua Hsieh , Chen-Hua Yu , Chung-Shi Liu , Chih-Wei Lin
IPC: H01L23/31 , B29C45/14 , B29K63/00 , B29L31/34 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/29 , H01L23/367 , H01L23/498 , H01L23/538 , H01L25/065
CPC classification number: H01L23/3114 , H01L21/4853 , H01L21/486 , H01L21/565 , H01L21/566 , H01L23/295 , H01L23/3121 , H01L23/3135 , H01L23/3675 , H01L23/49816 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/81 , H01L24/95 , H01L25/0655 , B29C45/14655 , B29K2063/00 , B29K2995/0007 , B29L2031/3406 , H01L24/13 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13149 , H01L2224/13155 , H01L2224/16225 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2224/81192 , H01L2924/1431 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/19101 , H01L2924/3511
Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.
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公开(公告)号：US11424213B2
公开(公告)日：2022-08-23
申请号：US17017622
申请日：2020-09-10
Inventor： Mao-Yen Chang , Chih-Wei Lin , Hao-Yi Tsai , Kuo-Lung Pan , Chun-Cheng Lin , Tin-Hao Kuo , Yu-Chia Lai , Chih-Hsuan Tai
IPC: H01L23/00 , H01L25/00 , H01L21/56 , H01L23/538 , H01L25/18
Abstract: A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.
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公开(公告)号：US20170179083A1
公开(公告)日：2017-06-22
申请号：US15443679
申请日：2017-02-27
Inventor： Chun-Cheng Lin , Chung-Shi Liu , Kuei-Wei Huang , Cheng-Ting Chen , Wei-Hung Lin , Ming-Da Cheng
IPC: H01L25/065 , H01L25/00 , H01L21/768 , H01L23/31 , H01L21/56 , H01L23/498 , H01L21/48 , H01L23/00 , H01L21/027
CPC classification number: H01L25/0657 , H01L21/0273 , H01L21/486 , H01L21/56 , H01L21/76898 , H01L23/3128 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/105 , H01L25/50 , H01L2224/0231 , H01L2224/0239 , H01L2224/03452 , H01L2224/0401 , H01L2224/05083 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/1131 , H01L2224/11424 , H01L2224/1152 , H01L2224/1162 , H01L2224/11825 , H01L2224/11849 , H01L2224/13024 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13611 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16238 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01048 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/12042 , H01L2924/15311 , H01L2924/15321 , H01L2924/15747 , H01L2924/18161 , H01L2924/2064 , H01L2924/20641 , H01L2924/20642 , H01L2924/00014 , H01L2924/00
Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
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公开(公告)号：US20170154811A1
公开(公告)日：2017-06-01
申请号：US14953783
申请日：2015-11-30
Inventor： Cheng-Tar Wu , Chung-Shi Liu , Chih-Wei Lin , Hui-Min Huang , Chun-Cheng Lin , Ming-Da Cheng
IPC: H01L21/768 , H01L23/00 , H01L23/532
CPC classification number: H01L21/76834 , H01L21/56 , H01L21/76828 , H01L23/291 , H01L23/295 , H01L23/3114 , H01L23/3192 , H01L23/5328 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/02313 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05164 , H01L2224/05181 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/10125 , H01L2224/10126 , H01L2224/11462 , H01L2224/1191 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13184 , H01L2924/00014 , H01L2924/014
Abstract: A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to laterally encapsulate a portion of the interconnect.
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公开(公告)号：US09230935B2
公开(公告)日：2016-01-05
申请号：US14557227
申请日：2014-12-01
Inventor： Chun-Cheng Lin , Hsiu-Jen Lin , Cheng-Ting Chen , Wei-Yu Chen , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L23/02 , H01L23/00 , H01L23/498 , H01L25/10 , H01L25/065 , H01L25/00 , H05K3/34 , H05K3/40 , H01L25/07
CPC classification number: H01L24/16 , H01L23/49816 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/48 , H01L24/81 , H01L24/94 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/074 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/056 , H01L2224/05611 , H01L2224/05616 , H01L2224/06181 , H01L2224/111 , H01L2224/11334 , H01L2224/11849 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13216 , H01L2224/13224 , H01L2224/13239 , H01L2224/13244 , H01L2224/13247 , H01L2224/13255 , H01L2224/13284 , H01L2224/13309 , H01L2224/13317 , H01L2224/13318 , H01L2224/1332 , H01L2224/13338 , H01L2224/13349 , H01L2224/13355 , H01L2224/1336 , H01L2224/13366 , H01L2224/137 , H01L2224/13809 , H01L2224/13817 , H01L2224/13818 , H01L2224/1382 , H01L2224/13838 , H01L2224/13849 , H01L2224/13855 , H01L2224/1386 , H01L2224/13866 , H01L2224/14181 , H01L2224/1601 , H01L2224/16145 , H01L2224/16148 , H01L2224/16225 , H01L2224/16506 , H01L2224/1703 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/94 , H01L2224/96 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01322 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/384 , H05K3/3436 , H05K3/4015 , H05K2201/10515 , Y02P70/613 , H01L2224/81 , H01L2924/00 , H01L2924/014 , H01L2924/01032 , H01L2924/01015 , H01L2924/01058 , H01L2924/00012 , H01L2924/0105 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.
Abstract translation: 封装结构包括具有第一区域和第二区域的第一基板，形成在第一基板的第一区域上的凸块，与第一基板的第二区域接合的第一半导体管芯，以及半导体管芯封装 到第一底物。 凸块包括分散在金属结构中的金属结构和多个次要元件。 半导体管芯封装包括接合到凸块的连接器，并且第一半导体管芯位于半导体管芯封装和第一衬底之间。
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Patent Agency Ranking
公开(公告)号：US09082636B2
公开(公告)日：2015-07-14
申请号：US14523248
申请日：2014-10-24
Inventor： Chih-Wei Lin , Kuei-Wei Huang , Yu-Peng Tsai , Chun-Cheng Lin , Meng-Tse Chen , Chen-Hua Yu , Mirng-Ji Lii , Chung-Shi Liu , Bor-Ping Jang , Hsiu-Jen Lin , Wen-Hsiung Lu , Ming-Da Cheng , Wei-Hung Lin
IPC: H01L21/00 , H01L25/065 , H01L23/498 , H01L21/56 , H01L23/00 , H01L21/683 , H01L25/00 , H01L23/538 , H01L21/52 , H01L21/768 , H01L23/31 , H01L25/03 , H01L25/10
CPC classification number: H01L25/0657 , H01L21/52 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2221/68331 , H01L2221/68345 , H01L2221/68377 , H01L2224/0231 , H01L2224/0401 , H01L2224/04105 , H01L2224/06515 , H01L2224/09181 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16238 , H01L2224/73259 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/9202 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2924/14 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/15322 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2224/81 , H01L2224/03 , H01L2924/014 , H01L2924/00
Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.
Abstract translation: 公开了用于半导体器件的封装方法和结构。 在一个实施例中，封装的半导体器件包括具有第一表面和与第一表面相对的第二表面的再分配层（RDL）。 至少一个集成电路耦合到RDL的第一表面，并且多个金属凸块耦合到RDL的第二表面。 模制化合物设置在RDL的至少一个集成电路和第一表面上。
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公开(公告)号：US09073158B2
公开(公告)日：2015-07-07
申请号：US14096263
申请日：2013-12-04
Inventor： Meng-Tse Chen , Chun-Cheng Lin , Kuei-Wei Huang , Yu-Peng Tsai , Wei-Hung Lin , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L23/34 , B23Q3/18 , H01L21/50 , H01L23/00 , H01L21/56 , H01L23/498 , H01L23/538
CPC classification number: B23Q3/18 , H01L21/50 , H01L21/561 , H01L21/563 , H01L23/49827 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/75 , H01L24/81 , H01L24/83 , H01L2224/131 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/75733 , H01L2224/75744 , H01L2224/75754 , H01L2224/7598 , H01L2224/75983 , H01L2224/81191 , H01L2224/81815 , H01L2224/83104 , H01L2224/83862 , H01L2224/83868 , H01L2224/83874 , H01L2224/97 , H01L2924/3511 , Y10T29/41 , H01L2924/00 , H01L2924/00014 , H01L2224/81 , H01L2924/00012 , H01L2924/014
Abstract: A method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component. A through-opening is in the lower jig and under the first package component. The underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening.
Abstract translation: 一种方法包括在第一包装部件和第二包装部件之间分配底部填充物，其中第一包装部件被放置在下部夹具上，并且第二包装部件结合到第一包装部件上。 通孔位于下夹具中并在第一包装部件下方。 底部填充物被固化，其中在固化底部填充物的步骤期间，施加力以使第一包装部件变平。 通过执行选自抽真空和通过通孔的空气吹扫的动作来施加力。
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公开(公告)号：US20140264849A1
公开(公告)日：2014-09-18
申请号：US14164673
申请日：2014-01-27
Inventor： Yu-Feng Chen , Han-Ping Pu , Chun-Hung Lin , Chun-Cheng Lin , Ming-Da Cheng , Kai-Chiang Wu
IPC: H01L23/00
CPC classification number: H01L23/3128 , H01L21/56 , H01L24/81 , H01L25/105 , H01L25/50 , H01L2224/131 , H01L2224/13147 , H01L2224/16237 , H01L2224/2919 , H01L2224/48227 , H01L2224/73204 , H01L2224/81815 , H01L2224/83102 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/014 , H01L2924/0665
Abstract: A device comprises a bottom package mounted on a printed circuit board, wherein the bottom package comprises a plurality of first bumps formed between the bottom package and the printed circuit board, a first underfill layer formed between the printed circuit board and the bottom package, a semiconductor die mounted on the bottom package and a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps and the top package and the bottom package form a ladder shaped structure. The device further comprises a second underfill layer formed between the bottom package and the top package, wherein the second underfill layer is formed of a same material as the first underfill layer.
Abstract translation: 一种装置包括安装在印刷电路板上的底部封装，其中底部封装包括形成在底部封装和印刷电路板之间的多个第一凸块，形成在印刷电路板和底部封装之间的第一底部填充层， 安装在底部封装上的半导体管芯和封装在底部封装上的顶部封装，其中顶部封装包括多个第二凸起，顶部封装和底部封装形成梯形结构。 该装置还包括形成在底部封装和顶部封装之间的第二底部填充层，其中第二底部填充层由与第一底部填充层相同的材料形成。
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公开(公告)号：US20240047446A1
公开(公告)日：2024-02-08
申请号：US17882626
申请日：2022-08-08
Inventor： Mao-Yen Chang , Chun-Cheng Lin , Chih-Wei Lin , Yi-Da Tsai , Hsaing-Pin Kuan , Chih-Chiang Tsao , Hsuan-Ting Kuo , Hsiu-Jen Lin , Yu-Chia Lai , Kuo-Lung Pan , Hao-Yi Tsai , Ching-Hua Hsieh
IPC: H01L25/18 , H01L23/00 , H01R12/57 , H01L25/065 , H01L25/00
CPC classification number: H01L25/18 , H01L24/19 , H01L24/95 , H01R12/57 , H01L24/13 , H01L25/0652 , H01L24/20 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/50 , H01L24/11 , H01L2224/19 , H01L2224/95001 , H01L2224/214 , H01L2224/2101 , H01L2224/81815 , H01L2224/81201 , H01L2224/81862 , H01L2224/81193 , H01L2224/81906 , H01L2224/1403 , H01L2224/14517 , H01L2224/14505 , H01L2224/1319 , H01L2924/0665 , H01L2924/0635 , H01L2924/07025 , H01L2224/1329 , H01L2224/13386 , H01L2924/05442 , H01L2224/13155 , H01L2224/13164 , H01L2224/13144 , H01L2224/16108 , H01L2224/16238 , H01L2224/16059 , H01L2224/13016 , H01L2224/1607 , H01L2224/8192 , H01L2224/1131 , H01L2924/1427 , H01L2924/14361 , H01L2924/1432 , H01L2924/1433 , H01L2924/1431
Abstract: A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.
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公开(公告)号：US11848300B2
公开(公告)日：2023-12-19
申请号：US17857035
申请日：2022-07-03
Inventor： Mao-Yen Chang , Chih-Wei Lin , Hao-Yi Tsai , Kuo-Lung Pan , Chun-Cheng Lin , Tin-Hao Kuo , Yu-Chia Lai , Chih-Hsuan Tai
IPC: H01L21/56 , H01L23/538 , H01L25/18 , H01L23/00 , H01L25/00
CPC classification number: H01L24/73 , H01L21/568 , H01L23/5383 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/18 , H01L25/50 , H01L2224/16145 , H01L2224/17179 , H01L2224/17517 , H01L2224/26145 , H01L2224/32145 , H01L2224/73204 , H01L2224/81815 , H01L2224/83007 , H01L2224/92125
Abstract: A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.
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