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    Delamination sensor
    1.
    发明授权
    Delamination sensor 有权

    公开(公告)号：US12125810B2

    公开(公告)日：2024-10-22

    申请号：US18190361

    申请日：2023-03-27

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Hsuan Tai ,  Ming-Chung Wu ,  Kuo-Wen Chen ,  Hsiang-Tai Lu

    IPC: H01L23/58 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L23/585 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/528

    Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

    Manufacturing method of fingerprint sensor
    3.
    发明授权
    Manufacturing method of fingerprint sensor 有权

    公开(公告)号：US11847852B2

    公开(公告)日：2023-12-19

    申请号：US18086667

    申请日：2022-12-22

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo ,  Ying-Cheng Tseng

    IPC: G06K9/00 ,  G06V40/13 ,  H01L21/70

    CPC classification number: G06V40/1306 ,  G06V40/1329 ,  H01L21/70

    Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.

    DELAMINATION SENSOR
    5.
    发明公开
    DELAMINATION SENSOR 审中-公开

    公开(公告)号：US20230238340A1

    公开(公告)日：2023-07-27

    申请号：US18190361

    申请日：2023-03-27

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Hsuan Tai ,  Ming-Chung Wu ,  Kuo-Wen Chen ,  Hsiang-Tai Lu

    IPC: H01L23/58 ,  H01L23/528 ,  H01L23/522 ,  H01L23/498

    CPC classification number: H01L23/585 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/49816

    Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

    MANUFACTURING METHOD OF FINGERPRINT SENSOR
    6.
    发明申请
    MANUFACTURING METHOD OF FINGERPRINT SENSOR 有权

    公开(公告)号：US20230126259A1

    公开(公告)日：2023-04-27

    申请号：US18086667

    申请日：2022-12-22

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo ,  Ying-Cheng Tseng

    IPC: G06V40/13 ,  H01L21/70

    Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.

    Delamination sensor
    7.
    发明授权
    Delamination sensor 有权

    公开(公告)号：US11616029B2

    公开(公告)日：2023-03-28

    申请号：US17365699

    申请日：2021-07-01

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Hsuan Tai ,  Ming-Chung Wu ,  Kuo-Wen Chen ,  Hsiang-Tai Lu

    IPC: H01L23/58 ,  H01L23/528 ,  H01L23/522 ,  H01L23/498

    Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

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