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公开(公告)号：US20240047446A1
公开(公告)日：2024-02-08
申请号：US17882626
申请日：2022-08-08
发明人： Mao-Yen Chang , Chun-Cheng Lin , Chih-Wei Lin , Yi-Da Tsai , Hsaing-Pin Kuan , Chih-Chiang Tsao , Hsuan-Ting Kuo , Hsiu-Jen Lin , Yu-Chia Lai , Kuo-Lung Pan , Hao-Yi Tsai , Ching-Hua Hsieh
IPC分类号： H01L25/18 , H01L23/00 , H01R12/57 , H01L25/065 , H01L25/00
CPC分类号： H01L25/18 , H01L24/19 , H01L24/95 , H01R12/57 , H01L24/13 , H01L25/0652 , H01L24/20 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/50 , H01L24/11 , H01L2224/19 , H01L2224/95001 , H01L2224/214 , H01L2224/2101 , H01L2224/81815 , H01L2224/81201 , H01L2224/81862 , H01L2224/81193 , H01L2224/81906 , H01L2224/1403 , H01L2224/14517 , H01L2224/14505 , H01L2224/1319 , H01L2924/0665 , H01L2924/0635 , H01L2924/07025 , H01L2224/1329 , H01L2224/13386 , H01L2924/05442 , H01L2224/13155 , H01L2224/13164 , H01L2224/13144 , H01L2224/16108 , H01L2224/16238 , H01L2224/16059 , H01L2224/13016 , H01L2224/1607 , H01L2224/8192 , H01L2224/1131 , H01L2924/1427 , H01L2924/14361 , H01L2924/1432 , H01L2924/1433 , H01L2924/1431
摘要： A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.
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公开(公告)号：US11848300B2
公开(公告)日：2023-12-19
申请号：US17857035
申请日：2022-07-03
发明人： Mao-Yen Chang , Chih-Wei Lin , Hao-Yi Tsai , Kuo-Lung Pan , Chun-Cheng Lin , Tin-Hao Kuo , Yu-Chia Lai , Chih-Hsuan Tai
IPC分类号： H01L21/56 , H01L23/538 , H01L25/18 , H01L23/00 , H01L25/00
CPC分类号： H01L24/73 , H01L21/568 , H01L23/5383 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/18 , H01L25/50 , H01L2224/16145 , H01L2224/17179 , H01L2224/17517 , H01L2224/26145 , H01L2224/32145 , H01L2224/73204 , H01L2224/81815 , H01L2224/83007 , H01L2224/92125
摘要： A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.
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公开(公告)号：US20230335523A1
公开(公告)日：2023-10-19
申请号：US17719390
申请日：2022-04-13
发明人： Jen-Jui Yu , Chih-Chiang Tsao , Hsuan-Ting Kuo , Mao-Yen Chang , Hsiu-Jen Lin , Ching-Hua Hsieh , Hao-Jan Pei
IPC分类号： H01L23/00 , H01L23/498 , H01L25/18 , H01L23/367
CPC分类号： H01L24/16 , H01L23/49822 , H01L24/13 , H01L24/29 , H01L24/73 , H01L25/18 , H01L23/367 , H01L24/81 , H01L2224/16227 , H01L2224/13109 , H01L2224/32225 , H01L2224/73204 , H01L2224/13113 , H01L2224/13139 , H01L2224/13147 , H01L2224/81815 , H01L2224/92125
摘要： A semiconductor package includes a substrate, a semiconductor device over the substrate and a plurality of solder joint structures bonded between the semiconductor device and the substrate, wherein each of the plurality of solder joint structures includes, by weight percent, 2% to 23% of Indium (In).
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公开(公告)号：US20230068263A1
公开(公告)日：2023-03-02
申请号：US17460319
申请日：2021-08-30
发明人： Mao-Yen Chang , Yu-Chia Lai , Cheng-Shiuan Wong , Ting Hao Kuo , Ching-Hua Hsieh , Hao-Yi Tsai , Kuo-Lung Pan , Hsiu-Jen Lin
IPC分类号： H01L23/00 , H01L21/56 , H01L23/58 , H01L23/544
摘要： A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.
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公开(公告)号：US12107064B2
公开(公告)日：2024-10-01
申请号：US17719390
申请日：2022-04-13
发明人： Jen-Jui Yu , Chih-Chiang Tsao , Hsuan-Ting Kuo , Mao-Yen Chang , Hsiu-Jen Lin , Ching-Hua Hsieh , Hao-Jan Pei
IPC分类号： H01L23/00 , H01L23/367 , H01L23/498 , H01L25/18
CPC分类号： H01L24/16 , H01L23/367 , H01L23/49822 , H01L24/13 , H01L24/29 , H01L24/73 , H01L24/81 , H01L25/18 , H01L2224/13109 , H01L2224/13113 , H01L2224/13139 , H01L2224/13147 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81815 , H01L2224/92125
摘要： A semiconductor package includes a substrate, a semiconductor device over the substrate and a plurality of solder joint structures bonded between the semiconductor device and the substrate, wherein each of the plurality of solder joint structures includes, by weight percent, 2% to 23% of Indium (In).
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公开(公告)号：US20240203936A1
公开(公告)日：2024-06-20
申请号：US18592523
申请日：2024-03-01
发明人： Mao-Yen Chang , Yu-Chia Lai , Cheng-Shiuan Wong , Ting Hao Kuo , Ching-Hua Hsieh , Hao-Yi Tsai , Kuo-Lung Pan , Hsiu-Jen Lin
IPC分类号： H01L23/00 , H01L21/56 , H01L23/544 , H01L23/58
CPC分类号： H01L24/96 , H01L21/561 , H01L21/568 , H01L23/544 , H01L23/562 , H01L23/585 , H01L24/24 , H01L24/82 , H01L24/73 , H01L2223/5442 , H01L2223/54426 , H01L2224/24137 , H01L2224/24146 , H01L2224/24265 , H01L2224/73204 , H01L2224/73209 , H01L2224/73217 , H01L2224/82005 , H01L2224/82947
摘要： A semiconductor structure includes a functional die, a dummy die, a conductive feature, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The conductive feature is electrically connected to the functional die. The seal ring is disposed aside the conductive feature. The alignment mark is disposed between the seal ring and the conductive feature, and the alignment mark is electrically isolated from the dummy die, the conductive feature and the seal ring.
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公开(公告)号：US20240071981A1
公开(公告)日：2024-02-29
申请号：US18499242
申请日：2023-11-01
发明人： Mao-Yen Chang , Chih-Wei Lin , Hao-Yi Tsai , Kuo-Lung Pan , Chun-Cheng Lin , Tin-Hao Kuo , Yu-Chia Lai , Chih-Hsuan Tai
IPC分类号： H01L23/00 , H01L21/56 , H01L23/538 , H01L25/00 , H01L25/18
CPC分类号： H01L24/73 , H01L21/568 , H01L23/5383 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/18 , H01L25/50 , H01L2224/16145 , H01L2224/17179 , H01L2224/17517 , H01L2224/26145 , H01L2224/32145 , H01L2224/73204 , H01L2224/81815 , H01L2224/83007 , H01L2224/92125
摘要： A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.
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公开(公告)号：US20210305212A1
公开(公告)日：2021-09-30
申请号：US17315381
申请日：2021-05-10
发明人： Wei-Kang Hsieh , Hung-Yi Kuo , Hao-Yi Tsai , Kuo-Lung Pan , Ting Hao Kuo , Yu-Chia Lai , Mao-Yen Chang , Po-Yuan Teng , Shu-Rong Chun
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
摘要： A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.
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公开(公告)号：US20240063075A1
公开(公告)日：2024-02-22
申请号：US17890210
申请日：2022-08-17
发明人： Pavithra Sriram , Kuo-Lung Pan , Po-Yuan Teng , Cheng-Chieh Wu , Mao-Yen Chang , Yu-Chia Lai , Shu-Rong Chun , Hao-Yi Tsai
IPC分类号： H01L23/367 , H01L25/065 , H01L25/10 , H01L21/56 , H01L23/31
CPC分类号： H01L23/367 , H01L25/0655 , H01L25/105 , H01L21/563 , H01L21/565 , H01L23/3135 , H01L24/16
摘要： A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.
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公开(公告)号：US11646296B2
公开(公告)日：2023-05-09
申请号：US17315381
申请日：2021-05-10
发明人： Wei-Kang Hsieh , Hung-Yi Kuo , Hao-Yi Tsai , Kuo-Lung Pan , Ting Hao Kuo , Yu-Chia Lai , Mao-Yen Chang , Po-Yuan Teng , Shu-Rong Chun
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
CPC分类号： H01L25/0657 , H01L24/02 , H01L24/13 , H01L24/14 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L25/50 , H01L2224/02373 , H01L2224/02375 , H01L2224/02377 , H01L2224/13024 , H01L2224/14131 , H01L2224/14132 , H01L2224/14134 , H01L2224/24147 , H01L2224/25171 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2225/06527 , H01L2225/06562
摘要： A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.
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