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53 条记录 (耗时 0.032 秒)

    Direct access to low-latency memory
    22.
    发明授权
    Direct access to low-latency memory 有权
    直接访问低延迟内存

    公开(公告)号：US07594081B2

    公开(公告)日：2009-09-22

    申请号：US11024002

    申请日：2004-12-28

    申请人： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

    发明人： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F9/3824 ,  G06F9/3885 ,  G06F12/0888

    摘要： A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

    摘要翻译： 提供内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致存储器。 该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。 系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。 低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器，从而绕过高速缓存一致存储器。 非普通的加载/存储指令可以是协处理器指令。 存储器可以是低延迟型存储器。 处理器可以包括多个处理器核。

    Selective replication of data structures
    23.
    发明授权
    Selective replication of data structures 有权
    数据结构的选择性复制

    公开(公告)号：US07558925B2

    公开(公告)日：2009-07-07

    申请号：US11335189

    申请日：2006-01-18

    申请人： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler

    发明人： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler

    IPC分类号： G06F12/02

    CPC分类号： G06F12/06 ,  G06F12/0653 ,  G06F2212/174

    摘要： Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data structures that are loaded (i.e., read) more often than they are stored (i.e., written).

    摘要翻译： 提供了用于在低延迟存储器中选择性地复制数据结构的方法和装置。 存储器包括被配置为存储相同数据结构的复制副本的多个单独存储体。 在接收到访问所存储的数据结构的请求时，低延迟存储器访问控制器选择存储体之一，然后从所选存储体存取所存储的数据。 可以使用比较不同存储体的相对可用性的温度计技术来实现存储体的选择。 受益于所产生的效率的示例性数据结构包括确定性有限自动机（DFA）图和与它们被存储（即，写入）相比更加加载（即读）的其他数据结构。

    Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature
    24.
    发明授权
    Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature 失效

    公开(公告)号：US07024533B2

    公开(公告)日：2006-04-04

    申请号：US10441451

    申请日：2003-05-20

    申请人： Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

    发明人： Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1689

    摘要： A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

    Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature
    25.
    发明授权
    Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature 失效
    同步多个偏斜源同步数据通道与自动初始化功能的机制

    公开(公告)号：US06636955B1

    公开(公告)日：2003-10-21

    申请号：US09652480

    申请日：2000-08-31

    申请人： Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

    发明人： Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

    IPC分类号： G06F1200

    CPC分类号： G06F13/1689

    摘要： A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself. Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

    摘要翻译： 计算机系统具有存储器控制器，其包括耦合到多个存储器通道的读取缓冲器。 存储器控制器有利地消除由存储器模块位于与存储器控制器不同的距离处引起的通道间偏移。 存储器控制器优选地包括用于每个存储器通道的通道接口和同步逻辑电路。 该电路包括读取和写入缓冲区，读取缓冲区的加载和卸载指针。 卸载指针逻辑生成卸载指针，加载指针逻辑生成加载指针。 指针优选地是根据两个不同的时钟信号递增的自由运行指针。 负载指针根据由存储器控制器产生的时钟增加，但是已经被引出到存储器模块和从存储器模块返回。 卸载指针根据计算机系统本身产生的时钟增加。 因为每个存储器通道的迹线长度可能不同，所以存储器模块将读数据提供给存储器控制器所花费的时间可能对于每个通道而言可能不同。 “偏斜”被定义为数据到达最早通道时和数据到达最新通道之间的时间差。 在系统初始化期间，指针是同步的。 初始化之后，这些指针用于加载和卸载读取缓冲区，从而消除内部信道偏移的影响。