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47 条记录 (耗时 0.016 秒)

    Random number generating device
    21.
    发明授权
    Random number generating device 失效
    随机数生成装置

    公开(公告)号：US07629609B2

    公开(公告)日：2009-12-08

    申请号：US12143124

    申请日：2008-06-20

    申请人： Tetsufumi Tanamoto ,  Shinobu Fujita

    发明人： Tetsufumi Tanamoto ,  Shinobu Fujita

    IPC分类号： H01L23/58

    CPC分类号： B82Y10/00 ,  G06F7/588 ,  H01L29/7888 ,  H04L9/0861

    摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

    摘要翻译： 目的是提供具有较小电路尺寸和较小输出偏置值的随机数产生装置。 随机数产生装置包括彼此平行布置的一对第一和第二电流路径，以及一对可互相交换电荷并位于第一和第二电流路径附近的第一和第二细颗粒 。

    METHOD AND APPARATUS FOR DESIGNING A THREE-DIMENSIONAL INTEGRATED CIRCUIT
    22.
    发明申请
    METHOD AND APPARATUS FOR DESIGNING A THREE-DIMENSIONAL INTEGRATED CIRCUIT 有权
    用于设计三维集成电路的方法和装置

    公开(公告)号：US20080244489A1

    公开(公告)日：2008-10-02

    申请号：US12047547

    申请日：2008-03-13

    申请人： Tetsufumi Tanamoto ,  Shinichi Yasuda ,  Shinobu Fujita

    发明人： Tetsufumi Tanamoto ,  Shinichi Yasuda ,  Shinobu Fujita

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/5068

    摘要： A method of designing a three-dimensional integrated circuit includes dividing two-dimensional layout data of a circuit formed on a semiconductor substrate into a plurality of layout block data in order to re-arrange in different layers, generating layout block data reversing one of the layout block data of two folded layers arranged vertically adjacent to each other, alternately arranging the reversed layout block data and non-reverse block layout data to form a plurality of layers vertically overlapped, selecting at least one from interconnects included in a plurality of layout block data of the circuit and ranging over plural layers so as to be mutually and functionally collected together with respect to at least one of time delay, interconnect length and block configuration, and re-arranging the selected interconnect using a via connecting an upper layer and an under layer of the folded interconnect.

    摘要翻译： 一种设计三维集成电路的方法包括将形成在半导体衬底上的电路的二维布局数据划分成多个布局块数据，以便重新排列在不同的层中，生成布局块数据， 交替布置反向布局块数据和非反向块布局数据以形成垂直重叠的多个层的两个折叠层的布局块数据，从包括在多个布局块中的互连中选择至少一个层 电路的数据并且跨越多个层，以便相对于时间延迟，互连长度和块配置中的至少一个而相互和功能地收集在一起，并且使用连接上层和第二层的通孔重新布置所选择的互连 折叠互连的下层。

    Random number generating device
    23.
    发明授权
    Random number generating device 有权
    随机数生成装置

    公开(公告)号：US07405423B2

    公开(公告)日：2008-07-29

    申请号：US10373874

    申请日：2003-02-27

    申请人： Tetsufumi Tanamoto ,  Shinobu Fujita

    发明人： Tetsufumi Tanamoto ,  Shinobu Fujita

    IPC分类号： H01L23/58

    CPC分类号： B82Y10/00 ,  G06F7/588 ,  H01L29/7888 ,  H04L9/0861

    摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

    摘要翻译： 目的是提供具有较小电路尺寸和较小输出偏置值的随机数产生装置。 随机数产生装置包括彼此并联布置的一对第一和第二电流路径，以及一对第一和第二细颗粒，其可以互相交换电荷，并且位于第一和第二电流路径附近 。

    Analog-to-digital converter for dividing reference voltage using plural variable resistors
    27.
    发明授权
    Analog-to-digital converter for dividing reference voltage using plural variable resistors 失效
    用于使用多个可变电阻器分压参考电压的模数转换器

    公开(公告)号：US08681034B2

    公开(公告)日：2014-03-25

    申请号：US13536085

    申请日：2012-06-28

    申请人： Takao Marukame ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    发明人： Takao Marukame ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    IPC分类号： H03M1/34

    CPC分类号： H03M1/1061 ,  H01L27/22 ,  H01L43/08 ,  H03M1/365

    摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit, and a plurality of comparators. The voltage generating unit is configured to divide a reference voltage by a plurality of variable resistors to generate a plurality of comparative voltages. Each of the plurality of comparator is configured to compare any one of the plurality of comparative voltages with an analog input voltage and output a digital signal based on a result of a comparison between the comparative voltage and the analog input voltage. Each of the plurality of variable resistors includes a plurality of variable resistive elements that are connected in series, and each of the plurality of variable resistive elements has a resistance value that is variably set according to an external signal.

    摘要翻译： 根据实施例，模数转换器包括电压产生单元和多个比较器。 电压产生单元被配置为通过多个可变电阻器分压参考电压以产生多个比较电压。 多个比较器中的每一个被配置为将多个比较电压中的任何一个与模拟输入电压进行比较，并且基于比较电压和模拟输入电压之间的比较结果输出数字信号。 多个可变电阻器中的每一个包括串联连接的多个可变电阻元件，并且多个可变电阻元件中的每一个具有根据外部信号可变地设置的电阻值。

    Analog-to-digital converter including differential pair circuit
    28.
    发明授权
    Analog-to-digital converter including differential pair circuit 失效
    模数转换器包括差分对电路

    公开(公告)号：US08681033B2

    公开(公告)日：2014-03-25

    申请号：US13535118

    申请日：2012-06-27

    申请人： Takao Marukame ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    发明人： Takao Marukame ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    IPC分类号： H03M1/34

    CPC分类号： H03M1/1061 ,  H03F3/45183 ,  H03F2203/45391 ,  H03F2203/45392 ,  H03F2203/45674 ,  H03K5/2481 ,  H03M1/365

    摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.

    摘要翻译： 根据实施例，模数转换器包括产生比较电压的电压产生单元; 和比较者。 每个比较器将比较电压中的任何一个与模拟输入电压进行比较，并输出数字信号。 每个比较器包括用于检测两个输入之间的电位差的差分对电路。 差分对电路包括第一和第二电路部分。 第一电路部分包括具有一个输入端的栅极的第一晶体管; 以及与第一晶体管串联连接的电阻器。 第二电路部分包括第二晶体管，其具有提供另一输入的栅极，并与第一晶体管形成差分对; 以及与第二晶体管串联连接的可变电阻器。 可变电阻器包括可变电阻元件，每个电阻元件具有根据控制信号可变地设置的电阻值。

    Memory circuit using spin MOSFETs, path transistor circuit with memory function, switching box circuit, switching block circuit, and field programmable gate array
    29.
    发明授权
    Memory circuit using spin MOSFETs, path transistor circuit with memory function, switching box circuit, switching block circuit, and field programmable gate array 有权
    使用自旋MOSFET的存储电路，具有存储功能的路径晶体管电路，开关盒电路，开关块电路和现场可编程门阵列

    公开(公告)号：US08611143B2

    公开(公告)日：2013-12-17

    申请号：US13403308

    申请日：2012-02-23

    申请人： Hideyuki Sugiyama ,  Masato Oda ,  Shinobu Fujita ,  Tetsufumi Tanamoto ,  Mizue Ishikawa ,  Takao Marukame ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    发明人： Hideyuki Sugiyama ,  Masato Oda ,  Shinobu Fujita ,  Tetsufumi Tanamoto ,  Mizue Ishikawa ,  Takao Marukame ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    IPC分类号： G11C11/00

    CPC分类号： G11C5/148 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.

    摘要翻译： 根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七 连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。 第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。

    SPIN TRANSISTOR AND MEMORY
    30.
    发明申请
    SPIN TRANSISTOR AND MEMORY 有权
    旋转晶体管和存储器

    公开(公告)号：US20130075843A1

    公开(公告)日：2013-03-28

    申请号：US13526007

    申请日：2012-06-18

    申请人： Tomoaki Inokuchi ,  Takao Marukame ,  Tetsufumi Tanamoto ,  Hideyuki Sugiyama ,  Mizue Ishikawa ,  Yoshiaki Saito

    发明人： Tomoaki Inokuchi ,  Takao Marukame ,  Tetsufumi Tanamoto ,  Hideyuki Sugiyama ,  Mizue Ishikawa ,  Yoshiaki Saito

    IPC分类号： H01L29/82

    CPC分类号： H01L43/08 ,  H01L29/66984

    摘要： A spin transistor according to an embodiment includes: a first magnetic layer formed above a substrate and serving as one of a source and a drain; an insulating film having a lower face facing to an upper face of the first magnetic layer, an upper face opposed to the lower face, and a side face different from the lower and upper faces, the insulating film being formed on the upper face of the first magnetic layer and serving as a channel; a second magnetic layer formed on the upper face of the insulating film and serving as the other one of the source and the drain; a gate electrode formed along the side face of the insulating film; and a gate insulating film located between the gate electrode and the side face of the insulating film.

    摘要翻译： 根据实施例的自旋晶体管包括：形成在衬底上并用作源极和漏极之一的第一磁性层; 绝缘膜，其具有面向第一磁性层的上表面的下表面，与下表面相对的上表面，以及不同于下表面和上表面的侧面，绝缘膜形成在第一磁性层的上表面上 第一磁性层，作为通道; 第二磁性层，形成在绝缘膜的上表面上并用作源极和漏极中的另一个; 沿绝缘膜的侧面形成的栅电极; 以及位于绝缘膜的栅极和侧面之间的栅极绝缘膜。