公开(公告)号：US20250117326A1

公开(公告)日：2025-04-10

申请号：US18987237

申请日：2024-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishan GOVINDARAJAN ,  Mihir Narendra MODY ,  Prithvi Shankar YEYYADI ANANTHA

IPC: G06F12/02

Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a transaction handling block that dynamically maps the most frequently accessed data segments into faster access memory. The technique creates shadow copies of the most frequently accessed data segments in the faster access memory, which is associated with lower latency. Access frequencies of the data segments for which shadow copies are provided are updated dynamically based on use. The technique is flexible for different memory hierarchies.

公开(公告)号：US20240214511A1

公开(公告)日：2024-06-27

申请号：US18599324

申请日：2024-03-08

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra MODY ,  Brijesh JADAV ,  Gang HUA ,  Niraj NANDAN ,  Rajasekhar Reddy ALLU ,  Ankur ANKUR ,  Mayank MANGLA

IPC: H04N5/262 ,  G06T3/40 ,  G06T7/12 ,  G06T7/60 ,  G06T11/00

CPC classification number: H04N5/2628 ,  G06T3/40 ,  G06T7/12 ,  G06T7/60 ,  G06T11/00

Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.

公开(公告)号：US20230350811A1

公开(公告)日：2023-11-02

申请号：US18346309

申请日：2023-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Gregory Raymond SHURTZ ,  Mihir Narendra MODY ,  Charles Lance FUOCO ,  Donald E. STEISS ,  Jonathan Elliot BERGSAGEL ,  Jason A.T. JONES

IPC: G06F12/1027 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F2009/45583 ,  G06F2212/657

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US20230169689A1

公开(公告)日：2023-06-01

申请号：US17538268

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Gang HUA ,  Mihir Narendra MODY ,  Niraj NANDAN ,  Shashank DABRAL ,  Rajasekhar Reddy ALLU ,  Denis Roland BEAUDOIN

IPC: G06T7/90 ,  G06T1/20

CPC classification number: G06T7/90 ,  G06T1/20 ,  G06T2207/20208 ,  G06T2207/10024

Abstract: Techniques for image processing including receiving input image data, wherein the input image data includes data associated with a clear color channel, receiving a color offset value associated with a color channel, wherein color values for the color channel are not provided in the input image data, based on the color offset value, generating intermediate estimated color values for the color channel, wherein generating the intermediate estimated color values includes: clipping color values that have a magnitude greater than the color offset value, and adjusting color values that have a magnitude less than the color offset value based on the color offset value, applying a color correction function to the intermediate estimated color values based on the color offset value to determine color corrected estimated color values, and outputting the color corrected estimated color values.

公开(公告)号：US20230161675A1

公开(公告)日：2023-05-25

申请号：US18151543

申请日：2023-01-09

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY ,  Prithvi Shankar YEYYADI ANANTHA

IPC: G06F11/14

CPC classification number: G06F11/1497 ,  G06F2201/87

Abstract: An electronic device, comprising: a first component configured to transmit a first set of data to a second component by providing a first memory request specifying the first set of data for and an input memory address, and a transaction tracking unit coupled to a first transport interface, the transaction tracking unit configured to: receive the first memory request; transmit a second memory request that specifies at least a first portion of the first set of data, via the first transport interface, to the second component; receive a response to the second memory request from the second component; determine that the response corresponds to the second memory request; and provide, to the first component, an output response based on the received response to the second memory request.

公开(公告)号：US20230086775A1

公开(公告)日：2023-03-23

申请号：US18072813

申请日：2022-12-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY ,  Shashank DABRAL ,  Rajasekhar ALLU ,  Niraj NANDAN

IPC: H04N9/04 ,  G06T1/20 ,  H04N9/67

Abstract: An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.

公开(公告)号：US20230041617A1

公开(公告)日：2023-02-09

申请号：US17564975

申请日：2021-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY

IPC: G06F13/42 ,  G06F13/40 ,  G06F12/1027

Abstract: A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

公开(公告)号：US20230016766A1

公开(公告)日：2023-01-19

申请号：US17945225

申请日：2022-09-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat SAGAR ,  Mihir Narendra MODY ,  Anthony Joseph LELL ,  Gregory Raymond SHURTZ

IPC: B60R1/00 ,  H04N5/225

Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.

公开(公告)号：US20220206970A1

公开(公告)日：2022-06-30

申请号：US17697114

申请日：2022-03-17

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan GOVINDARAJAN ,  Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Mihir Narendra MODY

IPC: G06F13/20 ,  G06F13/42

Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.

公开(公告)号：US20220030202A1

公开(公告)日：2022-01-27

申请号：US17497560

申请日：2021-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY ,  Shashank DABRAL ,  Rajasekhar ALLU ,  Niraj NANDAN

IPC: H04N9/04 ,  G06T1/20 ,  H04N9/67

Abstract: An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.