公开(公告)号：US06586799B1

公开(公告)日：2003-07-01

申请号：US09325047

申请日：1999-06-03

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/66712 ,  H01L29/7395

摘要： A semiconductor device includes a semiconductor layer having a main surface (100a), a first region (101) of a first conductivity type, a second region (102) of a second conductivity type, and a third region (103) of the second conductivity type, the first region (101) and the second region (102) having a first boundary (101a) formed therebetween, the first boundary (101a) being perpendicular to the main surface (100a), the third region (103) being formed in the first region (101) in spaced apart relation to the second region (102), the third region (103) having a depth less than the depth of the first boundary (101a) from the main surface (100a); and a control electrode (201) insulated from and overlying the main surface (100a) and extending from the first boundary (101a) to a second boundary (101b) formed between the first region (101) and the third region (103). The semiconductor device improves a tradeoff between breakdown voltage and on-resistance. A method of manufacturing the semiconductor device is also provided.

摘要翻译： 半导体器件包括具有主表面（100a），第一导电类型的第一区域（101）和第二导电类型的第二区域（102）和第二导电类型的第三区域（103）的半导体层 所述第一区域（101）和所述第二区域（102）具有形成在其间的第一边界（101a），所述第一边界（101a）垂直于所述主表面（100a），所述第三区域（103）形成为 所述第一区域（101）与所述第二区域（102）间隔开，所述第三区域（103）的深度小于所述第一边界（101a）从所述主表面（100a）的深度; 和从第一边界（101a）延伸到形成在第一区域（101）和第三区域（103）之间的第二边界（101b）延伸的控制电极（201）。 半导体器件改善了击穿电压和导通电阻之间的折衷。 还提供了制造半导体器件的方法。

公开(公告)号：US06586780B1

公开(公告)日：2003-07-01

申请号：US08931688

申请日：1997-09-16

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L2974

CPC分类号： H01L27/0623 ,  H01L2924/0002 ,  H03K17/567 ,  H01L2924/00

摘要： A semiconductor device includes a p type semiconductor substrate, a first n type region formed at the semiconductor substrate, a first n channel DMOS transistor formed in the first n type region, a second n type region formed at the semiconductor substrate, a vertical type pnp bipolar transistor formed in the second n type region, and a second n channel DMOS transistor formed in the second n type region. The first n channel DMOS transistor has a drain for receiving a high power supply voltage (Vdc) and a source for supplying an output voltage (Vout). The bipolar transistor has a base connected to the gate of the first n channel DMOS transistor, an emitter connected to the source of the first n channel DMOS transistor, and a collector connected to the ground. The second n channel DMOS transistor has a drain connected to the gate of the first n channel DMOS transistor and a source connected to the ground.

摘要翻译： 半导体器件包括ap型半导体衬底，形成在半导体衬底上的第一n型区域，形成在第一n型区域中的第一n沟道DMOS晶体管，形成在半导体衬底处的第二n型区域，垂直型pnp双极型 形成在第二n型区域中的晶体管，以及形成在第二n型区域中的第二n沟道DMOS晶体管。 第一n沟道DMOS晶体管具有用于接收高电源电压（Vdc）的漏极和用于提供输出电压（Vout）的源极。 双极晶体管具有连接到第一n沟道DMOS晶体管的栅极的基极，连接到第一n沟道DMOS晶体管的源极的发射极和连接到地的集电极。 第二n沟道DMOS晶体管具有连接到第一n沟道DMOS晶体管的栅极的漏极和连接到地的源极。

公开(公告)号：US06573582B2

公开(公告)日：2003-06-03

申请号：US09986906

申请日：2001-11-13

申请人： Yasunori Yamashita ,  Fumitoshi Yamamoto ,  Tomohide Terashima

发明人： Yasunori Yamashita ,  Fumitoshi Yamamoto ,  Tomohide Terashima

IPC分类号： H01L27095

CPC分类号： H01L21/761 ,  H01L27/0766

摘要： A bipolar transistor is formed on a semiconductor substrate. A Schottky diode is formed in the collector region of the bipolar transistor. The collector region and the semiconductor substrate are isolated in potential from each other by potential isolating layers.

公开(公告)号：US06472710B2

公开(公告)日：2002-10-29

申请号：US09881805

申请日：2001-06-18

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L31113

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42364

摘要： A field MOS transistor having a high withstand voltage is disclosed. An island region of an epitaxial layer is surrounded by a heavily-doped isolation layer and a lightly-doped isolation layer formed thereon. A channel region is formed in the island region so as to assume the same doping level as that of the lightly-doped isolation layer. A region is formed below the island region so as to assume the same doping level as that of the heavily-doped isolation layer, thus supplying a back gate voltage to the transistor. The channel formation region is formed simultaneously with formation of the lightly-doped isolation layer, and the region below the island region is formed simultaneously with the heavily-doped isolation layer. As a result, manufacturing processes can be simplified.

公开(公告)号：US06376891B1

公开(公告)日：2002-04-23

申请号：US08684558

申请日：1996-07-19

申请人： Tatsuhiko Nagatani ,  Tomohide Terashima

发明人： Tatsuhiko Nagatani ,  Tomohide Terashima

IPC分类号： H01L2358

CPC分类号： H01L21/761 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/0922

摘要： In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage element region adjoined by a high breakdown voltage isolation region. A method for forming the high breakdown voltage isolation region complies with a Resurf condition by adjusting a thickness and an impurity concentration of the epitaxial layer. Thus, a high breakdown voltage semiconductor device and a manufacturing process therefor is provided, which includes a low breakdown voltage element region and a high breakdown voltage element region, and a high breakdown isolation region separates a high breakdown voltage region without impairing the characteristics of an element formed on the low breakdown voltage element region.

公开(公告)号：US06344678B1

公开(公告)日：2002-02-05

申请号：US09520000

申请日：2000-03-06

申请人： Fumitoshi Yamamoto ,  Tomohide Terashima

发明人： Fumitoshi Yamamoto ,  Tomohide Terashima

IPC分类号： H01L27082

CPC分类号： H01L29/0804 ,  H01L29/7322

摘要： An n− epitaxial layer serving as a collector region is formed on a p-type silicon substrate. A p diffusion layer serving as a base region is formed on the n− epitaxial layer. An n− diffusion layer and an n+ diffusion layer defining an emitter region are formed on the p diffusion layer. A p+ diffusion layer serving as a base contact region for attaining contact with the p diffusion layer is formed with a prescribed interval between the same and the emitter region. Thus obtained is a semiconductor device comprising a transistor suppressing dispersion of a current amplification factor.

摘要翻译： 在p型硅衬底上形成用作集电极区的n外延层。 在n外延层上形成用作基极区的p扩散层。 在p扩散层上形成限定发射极区的n-扩散层和n +扩散层。 用作与p扩散层接触的基极接触区域的p +扩散层在其与发射极区域之间以规定的间隔形成。 这样获得的是包括抑制电流放大因子的色散的晶体管的半导体器件。

公开(公告)号：US06191466B1

公开(公告)日：2001-02-20

申请号：US09395939

申请日：1999-09-14

申请人： Yasunori Yamashita ,  Tomohide Terashima ,  Fumitoshi Yamamoto

发明人： Yasunori Yamashita ,  Tomohide Terashima ,  Fumitoshi Yamamoto

IPC分类号： H01L21336

CPC分类号： H01L27/0611 ,  H01L21/761 ,  H01L29/8611

摘要： A semiconductor device which has few peripheral element malfunctions and superior performance is obtained. The semiconductor device includes a p-type buried layer on a main surface of a semiconductor substrate, an n-type cathode region provided on the p-type buried layer, and a p-type anode region in contact with the side surface of the n-type cathode region, the p-type buried layer being higher than the p-type anode region in acceptor content, and the p-type buried layer being in contact with the bottom surfaces of the anode and cathode regions.

摘要翻译： 获得了具有极少的外围元件故障和优异性能的半导体器件。 半导体器件包括在半导体衬底的主表面上的p型掩埋层，设置在p型掩埋层上的n型阴极区域和与n型阴极区域接触的p型阳极区域 型阴极区，p型埋层比受体含量高于p型阳极区，p型掩埋层与阳极和阴极区的底表面接触。

公开(公告)号：US5889310A

公开(公告)日：1999-03-30

申请号：US854088

申请日：1997-05-09

申请人： Tomohide Terashima ,  Kazuhiro Shimizu

发明人： Tomohide Terashima ,  Kazuhiro Shimizu

IPC分类号： H01L27/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7816 ,  H01L27/0629 ,  H01L27/0635 ,  H01L29/1087 ,  H01L29/7801 ,  H01L29/0878 ,  H01L2924/0002

摘要： A high breakdown voltage pch-MOSFET having a breakdown voltage of 150V or more and a control element controlling the same are formed in a common n.sup.- epitaxial layer. Only an n-type region of n.sup.- epitaxial layer is distributed at a region located between the high breakdown voltage pch-MOSFET and the control element and extending along the substrate surface. A semiconductor device thus formed achieves a good throughput and reduces a required chip area.

摘要翻译： 具有150V或更高的击穿电压的高击穿电压pch-MOSFET和控制其的控制元件形成在共同的n-外延层中。 仅n型区域的n型外延层分布在位于高击穿电压pch-MOSFET与控制元件之间的区域上并且沿衬底表面延伸。 这样形成的半导体器件实现了良好的吞吐量并且减少了所需的芯片面积。

公开(公告)号：US5561077A

公开(公告)日：1996-10-01

申请号：US531750

申请日：1995-09-21

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L21/331 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/73 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L21/302

CPC分类号： H01L29/7824 ,  H01L29/0649 ,  H01L29/102 ,  H01L29/402 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/78603 ,  H01L29/8611 ,  H01L29/0692 ,  H01L29/0696 ,  Y10S438/981

摘要： A high-breakdown voltage semiconductor device and a fabrication method are disclosed. A dielectric layer (3) dielectrically isolates a semiconductor substrate (1) from a n.sup.- type semiconductor layer (2). An n.sup.+ type semiconductor region (4) having a lower resistance than the n.sup.- type semiconductor layer (2) is formed as if surrounded by a p.sup.+ type semiconductor region (5). The dielectric layer (3) consists of a relatively thick first region (3a) and a relatively thin first region (3b). The n.sup.+ type semiconductor region (4), which is located above the first region (3a), occupies a narrower area than the first region (3a). Thus, by forming the dielectric layer thick immediately under the first semiconductor layer and controlling the thickness of the dielectric layer at other portions, the breakdown voltage of the semiconductor device is improved without curbing RESURF effect.

摘要翻译： 公开了一种高耐压半导体器件和制造方法。 电介质层（3）介电地将半导体衬底（1）与n型半导体层（2）隔离。 形成具有比n型半导体层（2）低的电阻的n +型半导体区域（4），好像被p +型半导体区域（5）包围。 电介质层（3）由较厚的第一区域（3a）和较薄的第一区域（3b）构成。 位于第一区域（3a）上方的n +型半导体区域（4）占据比第一区域（3a）窄的区域。 因此，通过在第一半导体层的正下方形成电介质层，并控制其它部分的电介质层的厚度，可以提高半导体器件的击穿电压，而不会抑制RESURF效应。

公开(公告)号：US5360746A

公开(公告)日：1994-11-01

申请号：US193742

申请日：1994-02-09

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/744 ,  H01L21/329 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L49/00

CPC分类号： H01L29/66356 ,  H01L29/7391 ,  Y10S257/914

摘要： Between electrodes (9) and (10) are formed a p.sup.+ substrate (2), an n.sup.- epitaxial layer (1) having a protruding portion (3), an n.sup.+ diffusion region (4) and p.sup.+ diffusion regions (13). Control electrodes (6) are formed on insulating films (5) on opposite sides of the protruding portion (3) and n.sup.+ diffusion region (4). The potential at the control electrodes (6) is increased or decreased with the potential at an electrode (10) increased relative to an electrode (9) to generate potential barrier or conductivity modulation in the n.sup.- epitaxial layer (1), whereby a semiconductor device turns off or on. Introduced holes are drawn through the p.sup.+ diffusion regions (13) when the semiconductor device turns off, to provide a small resistance and a short distance when the holes are drawn without changes in the area of the n.sup.+ diffusion region (4). This permits the semiconductor device to have small switching loss and high switching speed with a low ON-voltage.

摘要翻译： 在电极（9）和（10）之间形成有p +衬底（2），具有突出部分（3），n +扩散区域（4）和p +扩散区域（13）的n-外延层（1）。 控制电极（6）形成在突出部（3）和n +扩散区（4）的相对侧的绝缘膜（5）上。 控制电极（6）上的电位随着电极（10）上的电位相对于电极（9）而增加或减小，以在n外延层（1）中产生势垒或电导率调制，由此半导体 设备关闭或打开。 当半导体器件关闭时，引入的空穴通过p +扩散区域（13）被拉出，以便在不改变n +扩散区域（4）的区域的情况下提供小的电阻和短的距离。 这允许半导体器件在低导通电压下具有小的开关损耗和高开关速度。