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    Semiconductor device and method of manufacturing the same
    21.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08546783B2

    公开(公告)日：2013-10-01

    申请号：US13541097

    申请日：2012-07-03

    申请人： Masahiro Moniwa ,  Nozomu Matsuzaki ,  Riichiro Takemura

    发明人： Masahiro Moniwa ,  Nozomu Matsuzaki ,  Riichiro Takemura

    IPC分类号： H01L31/032 ,  H01L45/00

    CPC分类号： H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

    摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.

    摘要翻译： 实现了容易形成相变膜的半导体器件及其制造方法，实现了高集成度和使用相变膜作为存储元件。 在形成一个存储单元的区域的MISFET与相邻的MISFET之间，每个MISFET源在绝缘半导体衬底的前表面相邻。 在两个MISFET的每个源极上的半导体衬底的前表面的平面图中形成具有比电阻率低的电阻率的相变膜和导电膜的多层结构，并且在其上层叠插塞。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上沿平行方向发送电流。

    Semiconductor device
    25.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07796426B2

    公开(公告)日：2010-09-14

    申请号：US12090375

    申请日：2005-10-17

    申请人： Osamu Tonomura ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki

    发明人： Osamu Tonomura ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C13/0004 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

    摘要： A technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the first-step voltage sets a temperature of the phase-change memory to a temperature at which the fastest nucleation is obtained; and the second pulse sets the temperature to a temperature at which the fastest crystal growth is obtained, thereby obtaining solid-phase growth of the phase-change material without melting. Moreover, the technique uses means for controlling the two-step voltage applied to the phase-change memory by a two-step voltage applied to a word line capable of reducing the drain current variation.

    摘要翻译： 一种能够提高设定操作速度的技术，其控制包括使用相变材料的存储单元的半导体器件的写入速度。 该技术使用用于设定要施加到相变材料的设定脉冲电压的装置以具有两个步骤：第一步骤电压将相变存储器的温度设置为获得最快成核的温度; 并且第二脉冲将温度设定为获得最快的晶体生长的温度，从而获得相变材料的固相生长而不熔化。 此外，该技术使用用于通过施加到能够减小漏极电流变化的字线的两级电压来控制施加到相变存储器的两级电压的装置。

    SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
    26.
    发明申请
    SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE 审中-公开
    半导体器件和半导体器件的制造方法

    公开(公告)号：US20090189136A1

    公开(公告)日：2009-07-30

    申请号：US12359594

    申请日：2009-01-26

    申请人： Nozomu Matsuzaki

    发明人： Nozomu Matsuzaki

    IPC分类号： H01L29/43 ,  H01L21/71 ,  H01L21/336

    CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

    摘要： A reliability of a semiconductor device having a phase-change memory is improved. A phase-change memory device has a bottom-electrode plug buried in an interlayer insulator that is provided on a main surface of a semiconductor substrate, an electric conductive material layer provided on an upper portion of the bottom-electrode plug and on the interlayer insulator, a phase-change material layer provided on the electric conductive material layer, and an upper-electrode plug provided on the phase-change material layer. The bottom-electrode plug and the upper-electrode plug which configure the phase-change memory device are provided at respective different positions in a plane of the semiconductor substrate.

    摘要翻译： 提高了具有相变存储器的半导体器件的可靠性。 相变存储器件具有掩埋在半导体衬底的主表面上的层间绝缘体中的底电极插塞，设置在底电极插塞的上部和层间绝缘体上的导电材料层 设置在导电材料层上的相变材料层和设置在相变材料层上的上电极插塞。 配置相变存储器件的底电极插头和上电极插头设置在半导体衬底的平面中的各个不同位置处。

    Semiconductor memory
    28.
    发明申请
    Semiconductor memory 审中-公开
    半导体存储器

    公开(公告)号：US20070170413A1

    公开(公告)日：2007-07-26

    申请号：US11596220

    申请日：2005-05-09

    申请人： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

    发明人： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

    IPC分类号： H01L29/04

    CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

    摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

    摘要翻译： 由于这种材料对高熔点金属和氧化硅膜具有低粘附性，所以相变存储器的制造过程已经受到硫属化物材料易于分层的问题的困扰。 此外，硫族化物材料具有低的热稳定性，因此在相变存储器的制造过程中倾向于升华。 根据本发明，在硫族化物材料层上和下方形成导电或绝缘粘合剂层以增强其分层强度。 此外，在硫族化物材料层的侧壁上形成由氮化物膜构成的保护膜，以防止硫属化物材料层的升华。

    Semiconductor device with a non-erasable memory and/or a nonvolatile memory
    29.
    发明申请
    Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效
    具有不可擦除存储器和/或非易失性存储器的半导体器件

    公开(公告)号：US20070159871A1

    公开(公告)日：2007-07-12

    申请号：US11715918

    申请日：2007-03-09

    申请人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

    发明人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

    IPC分类号： G11C16/06 ,  G11C11/34 ,  G11C7/10 ,  G11C11/00

    CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3454 ,  G11C2013/0092 ,  G11C2213/82

    摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

    摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。