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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20100096613A1

    公开(公告)日：2010-04-22

    申请号：US12522744

    申请日：2007-01-11

    申请人： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Yoshihisa Fujisaki ,  Masaharu Kinoshita ,  Yuichi Matsui

    发明人： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Yoshihisa Fujisaki ,  Masaharu Kinoshita ,  Yuichi Matsui

    IPC分类号： H01L45/00 ,  H01L21/02

    CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

    摘要： A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.

    摘要翻译： 相变存储器由形成在半导体衬底上的绝缘膜中的埋入通孔内的插塞形成，形成在绝缘膜上的界面层，其中埋入插塞，由硫化物层形成的记录层形成在 界面层和形成在记录层上的上接触电极。 根据电阻值变化存储信息的记录层由含有20原子％至38原子％的量的铟的含量为9原子％至28原子％的锗的硫属化物材料制成，3原子级的锑 ％〜18原子％，碲为42原子％〜63原子％，锗的含量大于或等于锑的含量。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US08618523B2

    公开(公告)日：2013-12-31

    申请号：US12302740

    申请日：2006-05-31

    申请人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

    发明人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

    IPC分类号： H01L47/00

    CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

    摘要： On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

    摘要翻译： 在嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽构成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层（52） 引入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过将绝缘膜（51）插入在记录层（52）和插塞（43）之间，可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。

    SEMICONDUCTOR DEVIC
    5.
    发明申请
    SEMICONDUCTOR DEVIC 失效
    半导体器件

    公开(公告)号：US20100012917A1

    公开(公告)日：2010-01-21

    申请号：US12302740

    申请日：2006-05-31

    申请人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

    发明人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

    IPC分类号： H01L47/00

    CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

    摘要： On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

    摘要翻译： 在嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽构成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层（52） 引入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过将绝缘膜（51）插入在记录层（52）和插塞（43）之间，可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。

    Semiconductor integrated circuit device and method of manufacturing the same
    7.
    发明申请
    Semiconductor integrated circuit device and method of manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US20060113520A1

    公开(公告)日：2006-06-01

    申请号：US11289410

    申请日：2005-11-30

    申请人： Naoki Yamamoto ,  Norikatsu Takaura ,  Yuichi Matsui ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Motoyasu Terao

    发明人： Naoki Yamamoto ,  Norikatsu Takaura ,  Yuichi Matsui ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Motoyasu Terao

    IPC分类号： H01L29/04

    CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

    摘要： Disclosed herein is a phase change memory semiconductor integrated circuit device using a chalcogenide film that solves a problem that the operation temperature capable of ensuring long time memory retention is low due to low phase change temperature is and, at the same time, a problem that power consumption of the device is high since a large current requires to rewrite memory information due to low resistance. A portion of constituent elements for a chalcogenide comprises nitride, oxide or carbide which are formed to the boundary between the chalcogenide film and a metal plug as an underlying electrode and to the grain boundary of chalcogenide crystals thereby increasing the phase change temperature and high Joule heat can be generated even by a small current by increasing the resistance of the film.

    摘要翻译： 这里公开了一种使用硫族化物膜的相变存储器半导体集成电路器件，其解决了由于相变温度低导致能够确保长时间存储保持的操作温度低的问题，并且同时存在功率 器件的消耗很高，因为大电流需要由于低电阻而重写存储器信息。 硫族化物的一部分组成元素包括氮化物，氧化物或碳化物，其形成于作为下伏电极的硫族化物膜和金属栓之间的边界以及硫族化物晶体的晶界上，从而增加相变温度和高焦耳热 即使通过增加膜的电阻也能通过小的电流产生。

    Semiconductor device and method of manufacturing the same
    8.
    发明申请
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20060105556A1

    公开(公告)日：2006-05-18

    申请号：US11272811

    申请日：2005-11-15

    申请人： Yuichi Matsui ,  Motoyasu Terao ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Naoki Yamamoto

    发明人： Yuichi Matsui ,  Motoyasu Terao ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Naoki Yamamoto

    IPC分类号： H01L21/20

    CPC分类号： C23C14/5806 ,  C23C14/0623 ,  C23C14/541 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

    摘要： The annealing process at 400° C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due to a decrease in adhesion, variations in resistance due to improper contact with a plug, and other undesirable events. After the chalcogenide material has been formed in an amorphous phase, post-annealing is conducted to form a (111)-oriented and columnarly structured face-centered cubic. This is further followed by high-temperature annealing to form a columnar, hexagonal closest-packed crystal. Use of this procedure makes it possible to suppress the growth of inclined crystal grains that causes voids, since crystal grains are formed in a direction perpendicular to the surface of an associated substrate.

    摘要翻译： 在相变存储器的布线处理所需的400℃以上所需的退火处理的问题在于，硫属化物材料中的晶粒沿倾斜方向生长，从而在储存层中产生空隙。 这些空隙又由于粘合力的降低而导致剥离，由于与插头的不正确接触导致的电阻变化以及其它不期望的事件。 在非晶态形成硫族化物材料之后，进行后退火以形成（111）取向和柱状结构的面心立方。 此后进一步进行高温退火以形成柱状，六边形最接近填充的晶体。 使用该方法可以抑制由于在垂直于相关衬底的表面的方向上形成晶粒而导致空隙的倾斜晶粒的生长。

    Semiconductor and semiconductor manufacturing arrangements having a chalcogenide layer formed of columnar crystal grains perpendicular to a main substrate surface
    9.
    发明授权
    Semiconductor and semiconductor manufacturing arrangements having a chalcogenide layer formed of columnar crystal grains perpendicular to a main substrate surface 有权
    具有由垂直于主衬底表面的柱状晶粒形成的硫族化物层的半导体和半导体制造布置

    公开(公告)号：US07638786B2

    公开(公告)日：2009-12-29

    申请号：US11272811

    申请日：2005-11-15

    申请人： Yuichi Matsui ,  Motoyasu Terao ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Naoki Yamamoto

    发明人： Yuichi Matsui ,  Motoyasu Terao ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Naoki Yamamoto

    IPC分类号： H01L29/02

    CPC分类号： C23C14/5806 ,  C23C14/0623 ,  C23C14/541 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

    摘要： The annealing process at 400° C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due to a decrease in adhesion, variations in resistance due to improper contact with a plug, and other undesirable events. After the chalcogenide material has been formed in an amorphous phase, post-annealing is conducted to form a (111)-oriented and columnarly structured face-centered cubic. This is further followed by high-temperature annealing to form a columnar, hexagonal closest-packed crystal. Use of this procedure makes it possible to suppress the growth of inclined crystal grains that causes voids, since crystal grains are formed in a direction perpendicular to the surface of an associated substrate.

    摘要翻译： 在相变存储器的布线处理所需的400℃以上所需的退火处理的问题在于，硫属化物材料中的晶粒沿倾斜方向生长，从而在储存层中产生空隙。 这些空隙又由于粘合力的降低而导致剥离，由于与插头的不正确接触导致的电阻变化以及其它不期望的事件。 在非晶态形成硫族化物材料之后，进行后退火以形成（111）取向和柱状结构的面心立方。 此后进一步进行高温退火以形成柱状，六边形最接近填充的晶体。 使用该方法可以抑制由于在垂直于相关衬底的表面的方向上形成晶粒而导致空隙的倾斜晶粒的生长。

    Semiconductor storage device and manufacturing method thereof
    10.
    发明申请
    Semiconductor storage device and manufacturing method thereof 审中-公开
    半导体存储装置及其制造方法

    公开(公告)号：US20060266992A1

    公开(公告)日：2006-11-30

    申请号：US11435934

    申请日：2006-05-18

    申请人： Yuichi Matsui ,  Tomio Iwasaki ,  Norikatsu Takaura ,  Kenzo Kurotsuchi

    发明人： Yuichi Matsui ,  Tomio Iwasaki ,  Norikatsu Takaura ,  Kenzo Kurotsuchi

    IPC分类号： H01L47/00

    CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675

    摘要： Since a chalcogenide material has low adhesion to a silicon oxide film, there is a problem in that it tends to separate from the film during the manufacturing step of a phase change memory. In addition, since the chalcogenide material has to be heated to its melting point or higher during resetting (amorphization) of the phase change memory, there is a problem of requiring extremely large rewriting current. An interfacial layer comprising an extremely thin insulator or semiconductor having the function as both an adhesive layer and a high resistance layer (thermal resistance layer) is inserted between chalcogenide material layer/interlayer insulative film and between chalcogenide material layer/plug.

    摘要翻译： 由于硫族化物材料对氧化硅膜的粘附性低，所以存在在相变存储器的制造工序中与膜分离的问题。 此外，由于在相变存储器的复位（非晶化）期间必须将硫属化物材料加热至其熔点以上，所以存在需要非常大的重写电流的问题。 在硫族化物材料层/层间绝缘膜之间和硫族化物材料层/插塞之间插入包含具有粘合剂层和高电阻层（耐热层）两者的极薄绝缘体或半导体的界面层。