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21.发明授权Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor 失效能够稳定地产生内部高电压的内部高压发生电路及其电路元件公开(公告)号：US06201437B1
公开(公告)日：2001-03-13
申请号：US09166171
申请日：1998-10-05
IPC分类号： G05F110
摘要： In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.
摘要翻译： 为了稳定地产生规定电平的高电压，响应用于将高电压与基准电压进行比较的激活信号而被激活的Vpp检测电路在控制下被强制地进入活动状态 初始控制电路。
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22.发明授权
公开(公告)号：US5382816A
公开(公告)日：1995-01-17
申请号：US69036
申请日：1993-05-28
申请人： Katsuyoshi Mitsui
发明人： Katsuyoshi Mitsui
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/423 , H01L29/78 , H01L29/10 , H01L29/68
CPC分类号： H01L29/7834 , H01L27/10841 , H01L29/4236
摘要： A semiconductor device allowing control of its threshold voltage without requiring change in the materials of its gate electrodes and suitable for high density integration is disclosed. The semiconductor device includes a p type monocrystalline silicon substrate 1 having a cylindrical portion with inner and outer surfaces and extending in a vertical direction. A first gate electrode 8 and a second gate electrode 10 are disposed at the inner surface and the outer surface of the cylindrical portion 2, respectively. A source/drain region 5 is formed on the top end of the cylindrical portion 2, while a source/drain region 3 is formed on the inner bottom surface of the cylindrical portion 2. Therefore, the cylindrical portion 2 can be utilized as a channel region of an MIS field effect transistor. The threshold voltage of the transistor can easily be controlled by applying separate voltages to the two gate electrodes, the first electrode and the second electrode.
摘要翻译： 公开了一种半导体器件，其允许控制其阈值电压，而不需要改变其栅电极的材料并适合于高密度集成。 半导体器件包括具有内表面和外表面并在垂直方向上延伸的圆柱形部分的p型单晶硅衬底1。 第一栅电极8和第二栅电极10分别设置在圆筒部2的内表面和外表面。 源极/漏极区域5形成在圆筒形部分2的顶端上，而源极/漏极区域3形成在圆柱形部分2的内底面上。因此，圆柱形部分2可以用作沟道 MIS场效应晶体管的区域。 通过向两个栅电极，第一电极和第二电极施加分开的电压，可以容易地控制晶体管的阈值电压。
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23.发明授权Method of fabricating semiconductor device having sidewall spacers and oblique implantation 失效制造具有顶板间隔的半导体器件和OBIIQUE植入的方法
公开(公告)号：US5217910A
公开(公告)日：1993-06-08
申请号：US779498
申请日：1991-10-24
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/823807 , H01L29/78
摘要： First, a low-concentration impurity layer is formed by obliquely implanting an n-type impurity at a prescribed angle with respect to the surface of a p-type semiconductor substrate, using a gate electrode formed on the semiconductor substrate as a mask. Thereafter a sidewall spacer is formed on the sidewall of the gate electrode, and then a medium-concentration impurity layer is formed by obliquely implanting an n-type impurity to the surface of the semiconductor substrate. Thereafter a high-concentration impurity layer is formed by substantially perpendicularly implanting an n-type impurity with respect to the surface of the semiconductor substrate. According to this method, the low-concentration impurity layer in source and drain regions having triple diffusion structures can be accurately overlapped with the gate electrode, with no requirement for heat treatment for thermal diffusion.
摘要翻译： 首先，使用形成在半导体衬底上的栅电极作为掩模，通过以相对于p型半导体衬底的表面以规定角度倾斜注入n型杂质来形成低浓度杂质层。 此后，在栅电极的侧壁上形成侧壁间隔物，然后通过向半导体衬底的表面倾斜注入n型杂质形成中等浓度杂质层。 此后，通过相对于半导体衬底的表面基本垂直地注入n型杂质来形成高浓度杂质层。 根据该方法，具有三重扩散结构的源极和漏极区域中的低浓度杂质层可以与栅电极精确重叠，而不需要热扩散热处理。
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24.发明授权Semiconductor memory device having voltage down convertor reducing current consumption 有权具有降压转换器的半导体存储器件减少电流消耗公开(公告)号：US06262931B1
公开(公告)日：2001-07-17
申请号：US09539893
申请日：2000-03-31
IPC分类号： G11C800
摘要： A control circuit & mode register outputs a signal responsive to each command to a VDC control circuit. The VDC control circuit outputs a signal PWRUP changing the quantity of a through current Ic of a comparator stored in a VDC in response to the command. The VDC control circuit internally generates a signal of which pulse width corresponds to a prescribed delay time, in response to input of the command. Therefore, activation of each bank may not be monitored but current consumption can be reduced by preferably controlling a power supply current while minimizing the number of delay circuits and wires.
摘要翻译： 控制电路和模式寄存器将响应于每个命令的信号输出到VDC控制电路。 VDC控制电路响应于该命令输出改变存储在VDC中的比较器的直流电流Ic的信号PWRUP。 VDC控制电路根据命令的输入内部产生脉冲宽度对应于规定的延迟时间的信号。 因此，通过优选地控制电源电流同时最小化延迟电路和电线的数量，可以不监视每个组的激活，而可以减少电流消耗。
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25.发明授权Semiconductor integrated circuit capable of rapidly rewriting data into memory cells 失效半导体集成电路能够将数据快速重写到存储单元中公开(公告)号：US06195298B1
公开(公告)日：2001-02-27
申请号：US09499734
申请日：2000-02-08
IPC分类号： G11C700
摘要： A semiconductor integrated circuit includes a node for the power supply voltage for array that is connected to a sense amplifier, a decoupling capacitance connected to the node for the power supply voltage for array, a voltage-down converter connected to the node for the power supply voltage for array and generating a largest voltage stored in a memory cell, and two voltage-down converters connected to the node for the power supply voltage for array and generating a voltage higher than the largest voltage, and boosts the voltage of the node for the power supply voltage for array to attain a voltage higher than the largest voltage in the stand-by state and activates the voltage-down converter generating the largest voltage in operation.
摘要翻译： 半导体集成电路包括用于连接到读出放大器的阵列的电源电压的节点，连接到用于阵列的电源电压的节点的去耦电容，连接到用于电源的节点的降压转换器 并且产生存储在存储单元中的最大电压，以及两个降压转换器，连接到节点，用于阵列的电源电压，并产生高于最大电压的电压，并将节点的电压升高为 用于阵列的电源电压以获得高于待机状态下的最大电压的电压，并激活在工作中产生最大电压的降压转换器。
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26.发明授权
公开(公告)号：US6091648A
公开(公告)日：2000-07-18
申请号：US145141
申请日：1998-09-01
IPC分类号： G11C11/413 , G05F1/56 , G11C5/14 , G11C7/06 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C7/00
摘要： A semiconductor integrated circuit includes a node for the power supply voltage for array that is connected to a sense amplifier, a decoupling capacitance connected to the node for the power supply voltage for array, a voltage-down converter connected to the node for the power supply voltage for array and generating a largest voltage stored in a memory cell, and two voltage-down converters connected to the node for the power supply voltage for array and generating a voltage higher than the largest voltage, and boosts the voltage of the node for the power supply voltage for array to attain a voltage higher than the largest voltage in the stand-by state and activates the voltage-down converter generating the largest voltage in operation.
摘要翻译： 半导体集成电路包括用于连接到读出放大器的阵列的电源电压的节点，连接到用于阵列的电源电压的节点的去耦电容，连接到用于电源的节点的降压转换器 并且产生存储在存储单元中的最大电压，以及两个降压转换器，连接到节点，用于阵列的电源电压，并产生高于最大电压的电压，并将节点的电压升高为 用于阵列的电源电压以获得高于待机状态下的最大电压的电压，并激活在工作中产生最大电压的降压转换器。
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27.发明授权Method of manufacturing an MIS device having lightly doped drain structure and conductive sidewall spacers 失效制造具有轻掺杂漏极结构和导电侧壁间隔物的MIS器件的方法
公开(公告)号：US5217913A
公开(公告)日：1993-06-08
申请号：US896535
申请日：1992-06-09
IPC分类号： H01L29/417 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/41775 , H01L29/7836
摘要： A MOS FET comprises a pair of source and drain impurity regions, a gate oxide film and a gate electrode. The source and drain regions have an LDD structure in which high concentration impurity regions and low concentration impurity regions are set off. The gate electrode is formed to extend over the channel region and contains sidewalls overlying the low concentration impurity regions. In addition, portions of the gate oxide film located between the sidewalls of the gate electrode and the respective low concentration impurity regions are formed to have a film thickness larger than that of the portion located between the gate electrode and the channel region. The thick portion of the oxide film underlying the gate sidewalls form a charge storage layer which reduces the resistance of the low impurity concentration region while minimizing the gate capacitance. In another example, conductive sidewall spacers are formed on sidewalls of a gate electrode through an insulating film. The sidewall spacers are connected with source and drain electrode connections or directly with source and drain impurity regions. Hot carriers generated near the drain are taken out from a gate insulating layer through conductive sidewall spacers. Accordingly, increase of the resistance due to trapped hot carriers can be prevented.
摘要翻译： MOS FET包括一对源极和漏极杂质区域，栅氧化物膜和栅极电极。 源区和漏区具有LDD结构，其中高浓度杂质区和低浓度杂质区被引出。 栅电极形成为在沟道区域上延伸并且包含覆盖低浓度杂质区的侧壁。 此外，位于栅电极的侧壁和各低浓度杂质区之间的栅极氧化膜的部分形成为具有大于位于栅电极和沟道区之间的部分的膜厚。 栅极侧壁下方的氧化膜的厚部形成电荷存储层，从而降低了低杂质浓度区域的电阻同时最小化栅极电容。 在另一示例中，通过绝缘膜在导电侧壁间隔物形成在栅电极的侧壁上。 侧壁间隔件与源极和漏极连接或直接与源极和漏极杂质区连接。 在漏极附近产生的热载流子通过导电侧壁间隔物从栅绝缘层中取出。 因此，可以防止由于被捕获的热载体引起的电阻的增加。
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28.发明授权
公开(公告)号：US5174881A
公开(公告)日：1992-12-29
申请号：US724488
申请日：1991-06-28
CPC分类号： C23C16/54 , C23C14/022 , C23C14/568 , C23C16/0236
摘要： A method of and an apparatus for removing a naturally grown oxide film and contaminants on the surface of a semiconductor substrate and then forming a thin film on the cleaned surface. The semiconductor substrate is placed in a pretreatment chamber and then hydrogen chloride gas is introduced into the chamber. Then, the semiconductor substrate is heated at a temperature between 200.degree..about.700.degree. C. and the surface of the semiconductor substrate is irradiated with ultraviolet rays, whereby the naturally grown oxide film and other contaminants on the semiconductor substrate can be removed. Then, a thin film is formed on the cleaned surface of the semiconductor substrate by a CVD method or a sputter method. According to this method, the naturally oxide film and other contaminants can be removed from the surface of the semiconductor substrate at a low temperature and the thin film can be formed on the cleaned surface. As a result, an interface structure between the semiconductor substrate and the thin film can be controlled to be in a preferable state.
摘要翻译： 一种用于去除半导体衬底表面上的天然生长的氧化物膜和污染物，然后在清洁表面上形成薄膜的方法和设备。 将半导体基板放置在预处理室中，然后将氯化氢气体引入室中。 然后，在200℃〜700℃的温度下加热半导体衬底，用紫外线照射半导体衬底的表面，由此可以除去半导体衬底上的天然生长的氧化膜和其它污染物。 然后，通过CVD法或溅射法在半导体衬底的清洁表面上形成薄膜。 根据该方法，可以在低温下从半导体基板的表面去除天然氧化膜和其它污染物，并且可以在清洁的表面上形成薄膜。 结果，可以将半导体衬底和薄膜之间的界面结构控制在优选的状态。
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公开(公告)号：US5146291A
公开(公告)日：1992-09-08
申请号：US399947
申请日：1989-08-31
IPC分类号： H01L29/417 , H01L29/78
CPC分类号： H01L29/41775 , H01L29/7835 , H01L29/7836 , Y10S257/90
摘要： A MOS FET comprises a pair of source and drain impurity regions, a gate oxide film and a gate electrode. The source and drain regions have an LDD structure in which high concentration impurity regions and low concentration impurity regions are set off. The gate electrode is formed to extend over the channel region and contains sidewalls overlying the low concentration impurity regions. In addition, portions of the gate oxide film located between the sidewalls of the gate electrode and the respective low concentration impurity regions are formed to have a film thickness larger than that of the portion located between the gate electrode and the channel region. The thick portion of the oxide film underlying the gate sidewalls form a charge storage layer which reduces the resistance of the low impurity concentration region while minimizing the gate capacitance. In another example, conductive sidewall spacers are formed on sidewalls of a gate electrode through an insulating film. The sidewall spacers are connected with source and drain electrode connections or directly with source and drain impurity regions. Hot carriers generated near the drain are taken out from a gate insulating layer through conductive sidewall spacers. Accordingly, increase of the resistance due to trapped hot carriers can be prevented.
摘要翻译： MOS FET包括一对源极和漏极杂质区域，栅氧化物膜和栅极电极。 源区和漏区具有LDD结构，其中高浓度杂质区和低浓度杂质区被引出。 栅电极形成为在沟道区域上延伸并且包含覆盖低浓度杂质区的侧壁。 此外，位于栅电极的侧壁和各低浓度杂质区之间的栅极氧化膜的部分形成为具有大于位于栅电极和沟道区之间的部分的膜厚。 栅极侧壁下方的氧化膜的厚部形成电荷存储层，从而降低了低杂质浓度区域的电阻同时最小化栅极电容。 在另一示例中，通过绝缘膜在导电侧壁间隔物形成在栅电极的侧壁上。 侧壁间隔件与源极和漏极连接或直接与源极和漏极杂质区连接。 在漏极附近产生的热载流子通过导电侧壁间隔物从栅绝缘层中取出。 因此，可以防止由于被捕获的热载体引起的电阻的增加。
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30.发明授权
公开(公告)号：US5075240A
公开(公告)日：1991-12-24
申请号：US509850
申请日：1990-04-17
IPC分类号： H01L21/265 , H01L21/266
CPC分类号： H01L21/266 , Y10S438/972
摘要： A conductive resist film is used as a mask in ion implantation. A portion of the conductive resist film is electrically connected to a semiconductor substrate. The charge of ions which enter the conductive resist film in ion implantation flows into the semiconductor substrate and dissipates therein.
摘要翻译： 在离子注入中使用导电抗蚀剂膜作为掩模。 导电抗蚀剂膜的一部分电连接到半导体衬底。 在离子注入中进入导电抗蚀剂膜的离子的电荷流入半导体衬底并在其中消散。
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