公开(公告)号：US5075240A

公开(公告)日：1991-12-24

申请号：US509850

申请日：1990-04-17

申请人： Yomiyuki Yama ,  Masatoshi Yasunaga ,  Katsuyoshi Mitsui ,  Ikuo Ogoh

发明人： Yomiyuki Yama ,  Masatoshi Yasunaga ,  Katsuyoshi Mitsui ,  Ikuo Ogoh

IPC分类号： H01L21/265 ,  H01L21/266

CPC分类号： H01L21/266 ,  Y10S438/972

摘要： A conductive resist film is used as a mask in ion implantation. A portion of the conductive resist film is electrically connected to a semiconductor substrate. The charge of ions which enter the conductive resist film in ion implantation flows into the semiconductor substrate and dissipates therein.

摘要翻译： 在离子注入中使用导电抗蚀剂膜作为掩模。 导电抗蚀剂膜的一部分电连接到半导体衬底。 在离子注入中进入导电抗蚀剂膜的离子的电荷流入半导体衬底并在其中消散。

公开(公告)号：US5217910A

公开(公告)日：1993-06-08

申请号：US779498

申请日：1991-10-24

申请人： Masahiro Shimizu ,  Katsuyoshi Mitsui ,  Yomiyuki Yama ,  Masatoshi Yasunaga

发明人： Masahiro Shimizu ,  Katsuyoshi Mitsui ,  Yomiyuki Yama ,  Masatoshi Yasunaga

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/78

摘要： First, a low-concentration impurity layer is formed by obliquely implanting an n-type impurity at a prescribed angle with respect to the surface of a p-type semiconductor substrate, using a gate electrode formed on the semiconductor substrate as a mask. Thereafter a sidewall spacer is formed on the sidewall of the gate electrode, and then a medium-concentration impurity layer is formed by obliquely implanting an n-type impurity to the surface of the semiconductor substrate. Thereafter a high-concentration impurity layer is formed by substantially perpendicularly implanting an n-type impurity with respect to the surface of the semiconductor substrate. According to this method, the low-concentration impurity layer in source and drain regions having triple diffusion structures can be accurately overlapped with the gate electrode, with no requirement for heat treatment for thermal diffusion.

摘要翻译： 首先，使用形成在半导体衬底上的栅电极作为掩模，通过以相对于p型半导体衬底的表面以规定角度倾斜注入n型杂质来形成低浓度杂质层。 此后，在栅电极的侧壁上形成侧壁间隔物，然后通过向半导体衬底的表面倾斜注入n型杂质形成中等浓度杂质层。 此后，通过相对于半导体衬底的表面基本垂直地注入n型杂质来形成高浓度杂质层。 根据该方法，具有三重扩散结构的源极和漏极区域中的低浓度杂质层可以与栅电极精确重叠，而不需要热扩散热处理。

公开(公告)号：US20110193640A1

公开(公告)日：2011-08-11

申请号：US13021047

申请日：2011-02-04

申请人： Tsukasa OISHI ,  Katsuyoshi Mitsui ,  Naoki Otani

发明人： Tsukasa OISHI ,  Katsuyoshi Mitsui ,  Naoki Otani

IPC分类号： H03L7/099

CPC分类号： H03B5/04 ,  H03L1/00 ,  H03L1/026

摘要： This invention provides a semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A temperature sensor detects the ambient temperature of the high speed OCO and a voltage sensor detects the operating voltage of the high speed OCO. The power supply module includes a BGR and generates the reference voltage, reference current, and operating voltage of the high speed OCO, based on a primary reference voltage which is output by the BGR. A flash memory stores a table specifying trimming codes for the reference voltage and reference current, related to an ambient temperature and an operating voltage of the high speed OCO. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to the detected ambient temperature and operating voltage.

摘要翻译： 本发明提供了一种半导体器件，其被设计为防止提供给高速OCO的参考电压和参考电流随着环境温度的变化和/或外部电源电压的变化而变化，并且减小电路面积 电源模块。 高速OCO输出高速时钟，其大小由参考电流和参考电压决定。 温度传感器检测高速OCO的环境温度，电压传感器检测高速OCO的工作电压。 电源模块包括BGR，并基于由BGR输出的主参考电压产生高速OCO的参考电压，参考电流和工作电压。 闪速存储器存储一个表格，该表格指定与环境温度和高速OCO的工作电压相关的参考电压和参考电流的修整代码。 逻辑单元根据与检测到的环境温度和工作电压相关的参考电压和参考电流调整代码调整参考电流和参考电压的值。

公开(公告)号：US07728678B2

公开(公告)日：2010-06-01

申请号：US12253636

申请日：2008-10-17

申请人： Katsuyoshi Mitsui

发明人： Katsuyoshi Mitsui

IPC分类号： H03L7/00 ,  H03L7/06

CPC分类号： H03L7/02 ,  H03L7/00

摘要： A semiconductor device includes a voltage control and oscillation circuit oscillating at a frequency according to a first control voltage to output an oscillation signal, a frequency/voltage conversion circuit receiving the oscillation signal from the voltage control and oscillation circuit and converting a frequency of the oscillation signal into a voltage, a control voltage generation circuit generating a new second control voltage having a level between that of the voltage converted by the frequency/voltage conversion circuit and that of a second control voltage generated previously, and an analog integration circuit integrating the second control voltage to generate the first control voltage and outputting the first control voltage to the voltage control and oscillation circuit.

摘要翻译： 一种半导体器件包括：电压控制和振荡电路，其以根据第一控制电压的频率振荡以输出振荡信号;频率/电压转换电路，从所述电压控制和振荡电路接收所述振荡信号，并转换所述振荡频率 信号转换为电压，产生具有在由频率/电压转换电路转换的电压与先前产生的第二控制电压的电压之间的电平的新的第二控制电压的控制电压产生电路以及将第二 控制电压产生第一控制电压并将第一控制电压输出到电压控制和振荡电路。

公开(公告)号：US5407867A

公开(公告)日：1995-04-18

申请号：US948528

申请日：1992-09-22

申请人： Masanobu Iwasaki ,  Hiromi Itoh ,  Akira Tokui ,  Katsuyoshi Mitsui ,  Katsuhiro Tsukamoto

发明人： Masanobu Iwasaki ,  Hiromi Itoh ,  Akira Tokui ,  Katsuyoshi Mitsui ,  Katsuhiro Tsukamoto

IPC分类号： C23C14/02 ,  C23C14/56 ,  C23C16/02 ,  C23C16/54 ,  H01L21/465

CPC分类号： C23C14/568 ,  C23C14/022 ,  C23C16/0236 ,  C23C16/54 ,  Y10S438/913

摘要： A method of and an apparatus for removing a naturally grown oxide film and contaminants on the surface of a semiconductor substrate and then forming a thin film on the cleaned surface. The semiconductor substrate is placed in a pretreatment chamber and then hydrogen chloride gas is introduced into the chamber. Then, the semiconductor substrate is heated at a temperature between 200.degree..about.700.degree. C. and the surface of the semiconductor substrate is irradiated with ultraviolet rays, whereby the naturally grown oxide film and other contaminants on the semiconductor substrate can be removed. Then, a thin film is formed on the cleaned surface of the semiconductor substrate by a CVD method or a sputter method. According to this method, the naturally oxide film and other contaminants can be removed from the surface of the semiconductor substrate at a low temperature and the thin film can be formed on the cleaned surface. As a result, an interface structure between the semiconductor substrate and the thin film can be controlled to be in a preferable state.

摘要翻译： 一种用于去除半导体衬底表面上的天然生长的氧化物膜和污染物，然后在清洁表面上形成薄膜的方法和设备。 将半导体基板放置在预处理室中，然后将氯化氢气体引入室中。 然后，在200℃〜700℃的温度下加热半导体衬底，用紫外线照射半导体衬底的表面，由此可以除去半导体衬底上的天然生长的氧化膜和其它污染物。 然后，通过CVD法或溅射法在半导体衬底的清洁表面上形成薄膜。 根据该方法，可以在低温下从半导体基板的表面去除天然氧化膜和其它污染物，并且可以在清洁的表面上形成薄膜。 结果，可以将半导体衬底和薄膜之间的界面结构控制在优选的状态。

公开(公告)号：US5378923A

公开(公告)日：1995-01-03

申请号：US909324

申请日：1992-07-06

申请人： Katsuyoshi Mitsui ,  Masahiro Shimizu

发明人： Katsuyoshi Mitsui ,  Masahiro Shimizu

IPC分类号： H01L27/12 ,  H01L21/338 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/812 ,  H01L29/06 ,  H01L29/784

CPC分类号： H01L29/78612

摘要： Holes generated by impact ionization in a SOI-MOS transistor is removed from the channel region to improve the breakdown voltage between the source and drain. A channel region of the SOI-MOS transistor is formed of a p type silicon layer. A drain region is formed of an n type silicon layer. A source region adjacent to the channel region includes an n type germanium layer. The forbidden energy band gap width of the germanium is smaller than that of the silicon. The n type germanium layer is formed in at least a portion of the source region. This layer is formed by ion-implanting germanium into a portion of the silicon layer, or removing a portion of the silicon layer, followed by growing a germanium layer in an epitaxial manner thereabove.

摘要翻译： 在SOI-MOS晶体管中通过冲击电离产生的孔从沟道区域去除以改善源极和漏极之间的击穿电压。 SOI-MOS晶体管的沟道区域由p型硅层形成。 漏区由n型硅层形成。 与沟道区相邻的源极区包括n型锗层。 锗的禁带宽度窄于硅。 n型锗层形成在源区的至少一部分中。 该层通过将锗离子注入到硅层的一部分中，或者去除硅层的一部分，然后以其外延方式生长锗层而形成。

公开(公告)号：US5296401A

公开(公告)日：1994-03-22

申请号：US973250

申请日：1992-11-09

申请人： Katsuyoshi Mitsui ,  Shigeki Komori

发明人： Katsuyoshi Mitsui ,  Shigeki Komori

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L29/78 ,  H01L21/70

CPC分类号： H01L29/42376 ,  H01L21/823864 ,  H01L29/78 ,  H01L29/7836

摘要： In a CMOS semiconductor device, a pMOS transistor and an nMOS transistor are formed on a single substrate. Each of the source/drain regions of the nMOS transistor and the pMOS transistor has LDD structure composed of a combination of a low concentration impurity region and a high concentration impurity region. The low concentration impurity region of the LDD structure of the pMOS transistor is formed in a self-align manner by ion implantation using a sidewall spacer with relatively thick film thickness. The low concentration impurity region of the LDD structure of the nMOS transistor is formed in a self-align manner by ion implantation using a relatively thin sidewall spacer as a mask. The sidewall spacer with thick film thickness of the pMOS transistor restrains that the channel between the source/drain regions is shortened due to thermal diffusion to cause punch through. As for the sidewall spacer of the nMOS transistor, its film thickness is selected to effectively restrain hot carrier effect in the vicinity of the drain and restrain degradation of current handling capability due to parasitic resistance to the minimum.

摘要翻译： 在CMOS半导体器件中，在单个衬底上形成pMOS晶体管和nMOS晶体管。 nMOS晶体管和pMOS晶体管的源极/漏极区域中的每一个具有由低浓度杂质区域和高浓度杂质区域的组合构成的LDD结构。 pMOS晶体管的LDD结构的低浓度杂质区域通过使用具有相对厚的膜厚度的侧壁间隔件的离子注入以自对准的方式形成。 nMOS晶体管的LDD结构的低浓度杂质区域通过使用相对较薄的侧壁间隔物作为掩模的离子注入以自对准的方式形成。 具有pMOS晶体管的厚膜厚度的侧壁隔离层限制了源极/漏极区域之间的沟道由于热扩散而被缩短以引起穿通。 对于nMOS晶体管的侧壁间隔物，其膜厚度被选择为有效地抑制在漏极附近的热载流子效应，并且抑制由寄生电阻降到最小的电流处理能力的劣化。

公开(公告)号：US5183771A

公开(公告)日：1993-02-02

申请号：US732541

申请日：1991-07-19

申请人： Katsuyoshi Mitsui ,  masahide Inuishi

发明人： Katsuyoshi Mitsui ,  masahide Inuishi

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7836 ,  Y10S257/90

摘要： In an MIS transistor of a type having LDD and salicide structures, the location of the boundary between the high and low impurity density source/drain regions and the positions of the salicide layers on the source/drain regions are independently controlled during fabrication using a double gate sidewall structure. An MIS transistor improved thereby has its boundary between the high and low impurity density source/drain regions at or displaced toward the control gate electrode with respect to the interface of the double gate sidewall structure.

摘要翻译： 在具有LDD和自对准硅化物结构的MIS晶体管中，高和低杂质浓度源极/漏极区域之间的边界位置和源极/漏极区域上的自对准硅化物层的位置在制造期间被独立地控制，使用双 门侧壁结构。 因此，改善的MIS晶体管相对于双栅极侧壁结构的界面在其与控制栅电极之间或之后的高杂质浓度源极/漏极区域之间具有边界。

公开(公告)号：US08963650B2

公开(公告)日：2015-02-24

申请号：US13571114

申请日：2012-08-09

申请人： Tsukasa Oishi ,  Katsuyoshi Mitsui ,  Naoki Otani

发明人： Tsukasa Oishi ,  Katsuyoshi Mitsui ,  Naoki Otani

IPC分类号： H03L1/00 ,  H03L1/02

CPC分类号： H03B5/04 ,  H03L1/00 ,  H03L1/026

摘要： A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.

摘要翻译： 设计用于防止提供给高速OCO的参考电压和参考电流随着环境温度的变化和/或外部电源电压的变化而变化并减小电源的电路面积的半导体器件 模块。 高速OCO输出高速时钟，其大小由参考电流和参考电压决定。 逻辑单元根据与检测到的环境温度和工作电压相关的参考电压和参考电流调整代码来调整参考电流和参考电压的值。

公开(公告)号：US06812748B2

公开(公告)日：2004-11-02

申请号：US10334005

申请日：2002-12-31

申请人： Katsuyoshi Mitsui

发明人： Katsuyoshi Mitsui

IPC分类号： H03K522

CPC分类号： H02M3/073 ,  H02M2001/0041

摘要： A VBB control circuit includes an intermediate potential generation circuit receiving a substrate potential VBB which is a negative potential and outputting a divided potential between a power supply potential INTVDD and a ground potential, and an inverter receiving the divided potential and determining whether the substrate potential is higher or lower than a desired value. A logic threshold value of the inverter is (½)×INTVDD. If a relationship of VBB=VREFB−(½)×INTVDD is satisfied, the divided potential accurately becomes (½)×INTVDD. Thereby, it is possible to realize a semiconductor device including a detection circuit which can arbitrarily select a detected potential of the VBB by changing VREFB and which is less influenced by a change in manufacturing conditions.

摘要翻译： VBB控制电路包括：中间电位产生电路，接收作为负电位的衬底电位VBB，并输出电源电位INTVDD与接地电位之间的分压电位;以及逆变器，接收分压电位，并确定衬底电位是否为 高于或低于期望值。 逆变器的逻辑门限值为（½）xINTVDD。 如果满足VBB = VREFB-（1/2）xINTVDD的关系，则分割电位精确地变为（1/2）xINTVDD。 因此，可以实现包括检测电路的半导体器件，该检测电路可以通过改变VREFB任意地选择VBB的检测电位，并且其受制造条件的变化的影响较小。