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    CONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    21.
    发明申请
    CONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190081000A1

    公开(公告)日：2019-03-14

    申请号：US15730744

    申请日：2017-10-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chen-Yi Weng ,  Shih-Che Huang ,  Ching-Li Yang ,  Chih-Sheng Chang

    IPC: H01L23/532 ,  H01L23/522

    Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
    23.
    发明申请
    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20250169368A1

    公开(公告)日：2025-05-22

    申请号：US18407360

    申请日：2024-01-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chau-Chung Hou ,  Kun-Ju Li ,  Hsin-Jung Liu ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Chih-Yueh Li ,  Hsin-Kuo Hsu ,  Ying-Chu Chen ,  Yi-Chen Hsiao

    IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/80

    Abstract: A method of forming a semiconductor structure is disclosed. A substrate is provided having a memory array area and a peripheral region. A memory structure is formed on the substrate in the memory array area. A step height is formed between the memory array area and the peripheral region. A dielectric layer is deposited. The dielectric layer covers the memory structure. A reverse etching process is performed to remove part of the dielectric layer from the memory array area, thereby forming an upwardly protruding wall structure along the perimeter of the memory array area, wherein the thickness of the dielectric layer in the memory array area increases from the central area of the memory array area to the periphery of the memory array area. A polishing process is performed on the dielectric layer to remove the upwardly protruding wall structure from the memory array area.

    Semiconductor structure and method for forming the same
    25.
    发明授权
    Semiconductor structure and method for forming the same 有权

    公开(公告)号：US12284812B2

    公开(公告)日：2025-04-22

    申请号：US18636306

    申请日：2024-04-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Chien-Ting Lin

    IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80

    Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

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