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    SEMICONDUCTOR POWER DEVICE
    21.
    发明申请
    SEMICONDUCTOR POWER DEVICE 有权
    半导体功率器件

    公开(公告)号：US20150137176A1

    公开(公告)日：2015-05-21

    申请号：US14083551

    申请日：2013-11-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Lun Hsu ,  Chung-Yi Chiu

    IPC: H01L29/739

    CPC classification number: H01L29/7395 ,  H01L29/0834

    Abstract: A semiconductor power device is provided, comprising a substrate of a first conductive type, a buffering layer of a second conductive type formed on the substrate, a voltage supporting layer formed on the buffering layer, and alternating sections of different conductive types formed at the substrate. The voltage supporting layer comprises first semiconductor regions of the first conductive type and second semiconductor regions of the second conductive type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged. The alternating section and the buffering layer form a segmented structure of alternated conductive types, which is used as an anode of the semiconductor device.

    Abstract translation: 提供了一种半导体功率器件，包括第一导电类型的衬底，形成在衬底上的第二导电类型的缓冲层，形成在缓冲层上的电压支撑层，以及形成在衬底上的不同导电类型的交替部分 。 电压支撑层包括第一导电类型的第一半导体区域和第二导电类型的第二半导体区域，其中第一半导体区域和第二半导体区域交替布置。 交替部分和缓冲层形成交替导电类型的分段结构，其用作半导体器件的阳极。

    MEMS structure and method of forming the same
    22.
    发明申请
    MEMS structure and method of forming the same 有权
    MEMS结构及其形成方法

    公开(公告)号：US20140367805A1

    公开(公告)日：2014-12-18

    申请号：US13917655

    申请日：2013-06-14

    Applicant: United Microelectronics Corp.

    Inventor： Li-Che Chen ,  Te-Yuan Wu ,  Chia-Huei Lin ,  Hui-Min Wu ,  Kun-Che Hsieh ,  Kuan-Yu Wang ,  Chung-Yi Chiu

    IPC: B81C1/00

    CPC classification number: B81B3/0075 ,  B81B2207/07 ,  B81C1/00246 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735

    Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.

    Abstract translation: 一种形成MEMS结构的方法，其中形成蚀刻停止层以埋入介电层内，并且在从背面蚀刻基板和介电层之间形成室时，蚀刻停止层 保护剩余的介电层。 如此形成的室在基板的背面具有开口，与开口相对的天花板和连接天花板的侧壁。 侧壁还可包括蚀刻停止层的一部分。

    RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    23.
    发明申请
    RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20240422989A1

    公开(公告)日：2024-12-19

    申请号：US18223043

    申请日：2023-07-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

    IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

    Abstract: A resistive memory device includes a dielectric layer, a trench, a first resistive switching element, a diode via structure, and a signal line structure. The trench is disposed in the dielectric layer. The first resistive switching element is disposed in the trench. The first resistive switching element includes a first bottom electrode, a first top electrode disposed above the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode. The diode via structure is disposed in the dielectric layer and located under the trench, and the diode via structure is connected with the first bottom electrode. The signal line structure is disposed in the trench, a part of the signal line structure is disposed on the first resistive switching element, and the signal line structure is electrically connected with the first top electrode.

    MANUFACTURING METHOD OF MEMORY DEVICE
    26.
    发明公开
    MANUFACTURING METHOD OF MEMORY DEVICE 审中-公开

    公开(公告)号：US20230413695A1

    公开(公告)日：2023-12-21

    申请号：US18239108

    申请日：2023-08-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    CPC classification number: H10N70/826 ,  H10N70/231 ,  H10N70/011 ,  H10B63/00

    Abstract: A manufacturing method of a memory device includes following steps. A memory unit including a first electrode, a second electrode, and a memory material layer is formed on a substrate. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A first spacer layer including a first portion, a second portion, and a third portion is formed on a sidewall of the memory unit. The first portion is disposed on a sidewall of the first electrode. The second portion is disposed on a sidewall of the second electrode. The third portion is disposed above the memory unit in the vertical direction and connected with the second portion. A thickness of the second portion in a horizontal direction is greater than that of the first portion in the horizontal direction.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    27.
    发明公开
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230378275A1

    公开(公告)日：2023-11-23

    申请号：US17844746

    申请日：2022-06-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

    IPC: H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L29/778

    CPC classification number: H01L29/2003 ,  H01L29/66462 ,  H01L29/205 ,  H01L29/7786

    Abstract: A semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, and a silicon-rich tensile stress layer. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer, and the silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A silicon-rich tensile stress layer is formed on the III-V compound barrier layer. An annealing process is performed after the silicon-rich tensile stress layer is formed. A part of silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer for forming a silicon-doped III-V compound barrier layer by the annealing process.

    METHOD OF SIMULATING 3D FEATURE PROFILE BY USING SEM IMAGE
    28.
    发明公开
    METHOD OF SIMULATING 3D FEATURE PROFILE BY USING SEM IMAGE 审中-公开

    公开(公告)号：US20230350381A1

    公开(公告)日：2023-11-02

    申请号：US17749176

    申请日：2022-05-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yen-Ting Pan ,  Chung-Yi Chiu

    IPC: G05B19/4099 ,  G06T7/13 ,  G06T7/73 ,  G03F7/20

    CPC classification number: G05B19/4099 ,  G06T7/13 ,  G06T7/73 ,  G03F7/705 ,  G06T2207/10061 ,  G06T2207/30148 ,  G05B2219/35134

    Abstract: A method of simulating a 3D feature profile by using a scanning electron microscope (SEM) image includes providing an SEM image. The SEM image includes a feature pattern within a material layer. The feature pattern includes an inner edge and an outer edge. The outer edge surrounds the inner edge. Then, the positions of the inner edge and the outer edge of the feature pattern are identified. Latter, a side edge region is defined based on the positions of the inner edge and the outer edge. Subsequently, a side edge model is generated automatically to simulate a profile of the feature pattern in the side edge region. Finally, a 3D feature profile is automatically output based on the position of the inner edge, the position of the outer edge, the thickness of the material layer and the side edge profile.

    MANUFACTURING METHOD OF MEMORY DEVICE
    29.
    发明申请
    MANUFACTURING METHOD OF MEMORY DEVICE 有权

    公开(公告)号：US20220406996A1

    公开(公告)日：2022-12-22

    申请号：US17377367

    申请日：2021-07-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

    IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

    Abstract: A manufacturing method of a memory device includes the following steps. Memory units are formed on a substrate. Each of the memory units includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a sidewall portion of the non-conformal spacer layer and a sidewall portion of the conformal spacer layer in the vertical direction.

    Method of forming a semiconductor device
    30.
    发明授权
    Method of forming a semiconductor device 有权

    公开(公告)号：US11488829B1

    公开(公告)日：2022-11-01

    申请号：US17337457

    申请日：2021-06-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuan-Ying Lai ,  Hsin-Yu Hsieh ,  Chang-Mao Wang ,  Chung-Yi Chiu

    IPC: H01L21/28 ,  H01L21/3213 ,  H01L29/49

    Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first device region and a second device region is provided. A metal nitride barrier layer is formed to cover the first device region and the second device region. A titanium layer is deposited on the metal nitride barrier layer. The titanium layer is selectively removed from the second device region, thereby exposing the metal nitride barrier layer in the second device region. The titanium layer in the first device region is transformed into a titanium nitride layer. The titanium nitride layer is a work function layer on the first device region.

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