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    Fin type electrostatic discharge protection device
    23.
    发明授权
    Fin type electrostatic discharge protection device 有权
    翅式静电放电保护装置

    公开(公告)号：US09368484B1

    公开(公告)日：2016-06-14

    申请号：US14723482

    申请日：2015-05-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Chun Chen ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7851

    Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

    Abstract translation: 翅片型ESD保护装置包括至少一个第一鳍片，至少一个第二鳍片和至少一个栅极结构。 第一翅片设置在半导体衬底上，源极触点接触第一鳍片。 第二鳍片设置在半导体衬底上，漏极接触件接触第二鳍片。 第一鳍片和第二鳍片分别在第一方向上延伸，并且第一鳍片与第二鳍片分离。 栅极结构设置在源极触点和漏极触点之间。 第一鳍片与漏极接触部分开，第二鳍片与源极接触部分离开。

    COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE
    24.
    发明申请
    COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE 有权
    补充金属氧化物半导体器件

    公开(公告)号：US20150123184A1

    公开(公告)日：2015-05-07

    申请号：US14071670

    申请日：2013-11-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chang-Tzu Wang ,  Yu-Chun Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H01L27/092 ,  H01L27/06 ,  H01L23/60 ,  H01L29/78

    CPC classification number: H01L27/0925 ,  H01L21/823892 ,  H01L27/0274 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/785

    Abstract: A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor.

    Abstract translation: CMOS器件包括衬底，pMOS晶体管和形成在衬底上的nMOS晶体管，以及门控二极管。 门控二极管包括形成在pMOS晶体管和nMOS晶体管之间的衬底上的浮置栅极和形成在衬底中以及在pMOS晶体管和nMOS晶体管之间的一对p掺杂区域和n掺杂区域。 在浮置栅极和nMOS晶体管之间形成n掺杂区域，并且在浮置栅极和pMOS晶体管之间形成p掺杂区域。

    Circuit selector of embedded magnetoresistive random access memory
    30.
    发明授权
    Circuit selector of embedded magnetoresistive random access memory 有权

    公开(公告)号：US11011575B2

    公开(公告)日：2021-05-18

    申请号：US16655251

    申请日：2019-10-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Sheng Feng ,  Yu-Chun Chen ,  Chiu-Jung Chiu

    IPC: H01L27/22 ,  G11C11/16 ,  H01L43/10 ,  H01F10/32 ,  H01L43/02

    Abstract: A circuit selector of embedded magnetoresistive random access memory (EMRAM) includes a transistor comprising a source/drain terminal coupled to a first magnetic tunneling junction (MTJ) and a second MTJ, a gate terminal, and a drain/source terminal coupled to a voltage source. Preferably, the first MTJ includes a first free layer, a first barrier layer, and a first pinned layer, in which the first free layer is coupled to the source/drain terminal and the first pinned layer is coupled to a first circuit. The second MTJ includes a second free layer, a second barrier layer, and a second pinned layer, in which the second pinned layer is coupled to the source/drain terminal and the second free layer is coupled to a second circuit.

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