公开(公告)号：US10276650B2

公开(公告)日：2019-04-30

申请号：US15927103

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/94

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

公开(公告)号：US20180190662A1

公开(公告)日：2018-07-05

申请号：US15854825

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Mei-Ling Chen ,  Chia-Lung Chang ,  Ching-Hsiang Chang ,  Jui-Min Lee ,  Tsun-Min Cheng ,  Lin-Chen Lu ,  Shih-Fang Tzou ,  Kai-Jiun Chang ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Chia-Chen Wu

IPC: H01L27/108 ,  H01L21/033 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L27/10885 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/28568 ,  H01L21/32139 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/53271 ,  H01L27/10823 ,  H01L27/10876

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following. A hard mask layer is formed on a metal stack by a chemical vapor deposition process importing nitrogen (N2) gases and then importing amonia (NH3) gases. The present invention also provides a bit line gate structure of a dynamic random access memory (DRAM) including a metal stack and a hard mask. The metal stack includes a polysilicon layer, a titanium layer, a titanium nitride layer, a first tungsten nitride layer, a tungsten layer and a second tungsten nitride layer stacked from bottom to top. The hard mask is disposed on the metal stack.

公开(公告)号：US09012300B2

公开(公告)日：2015-04-21

申请号：US13633104

申请日：2012-10-01

Applicant: United Microelectronics Corp.

Inventor： Wu-Sian Sie ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yu-Ting Li ,  Wei-Che Tsao ,  Yen-Ming Chen ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76229

Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

Abstract translation: 浅沟槽隔离的制造方法。 首先，提供基板，在基板上顺序地形成硬掩模层和图案化的光致抗蚀剂层，然后通过蚀刻工艺在基板中形成至少一个沟槽，去除硬掩模层。 然后，至少在沟槽中形成填料，然后对填料进行平面化处理。 由于仅在填料上进行平坦化处理，所以可以有效地避免凹陷现象。

公开(公告)号：US20140256115A1

公开(公告)日：2014-09-11

申请号：US14285645

申请日：2014-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Chia-Lung Chang ,  Jei-Ming Chen ,  Jui-Min Lee ,  Yuh-Min Lin

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L29/0649

Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.

Abstract translation: 半导体结构位于衬底的凹部中。 半导体结构包括衬垫，富硅层和填充材料。 衬垫位于凹槽的表面上。 富硅层位于衬套上。 填充材料位于富硅层上并填充凹槽。 此外，还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US20140213034A1

公开(公告)日：2014-07-31

申请号：US13752408

申请日：2013-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lung Chang ,  Chih-Chien Liu ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Jui-Min Lee ,  Keng-Jen Lin ,  Chin-Fu Lin

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76232

Abstract: A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer. A protective layer is formed to cover the trench and the hard mask layer. A first isolation material is filled into the trench. An etching process is performed to etch back part of the first isolation material.

Abstract translation: 形成隔离结构的方法包括以下步骤。 在基板上形成硬掩模层，并且在基板和硬掩模层中形成沟槽。 形成保护层以覆盖沟槽和硬掩模层。 第一隔离材料被填充到沟槽中。 执行蚀刻工艺以蚀刻第一隔离材料的一部分。

公开(公告)号：US20140134824A1

公开(公告)日：2014-05-15

申请号：US13677318

申请日：2012-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jei-Ming Chen ,  Wen-Yi Teng ,  Chia-Lung Chang ,  Chih-Chien Liu

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/3105 ,  H01L21/76229 ,  H01L21/76819 ,  H01L21/76826 ,  H01L21/76837

Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.

Abstract translation: 制造介电层的方法包括以下步骤。 首先，在基板上形成电介质层，对电介质层进行化学机械研磨（CMP）处理。 随后，在化学机械抛光工艺之后对电介质层进行表面处理工艺，并且表面处理工艺包括引入氧等离子体。

公开(公告)号：US08709901B1

公开(公告)日：2014-04-29

申请号：US13864277

申请日：2013-04-17

Applicant: United Microelectronics Corp.

Inventor： Chia-Lung Chang ,  Wu-Sian Sie ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Chih-Chien Liu ,  Jui-Min Lee ,  Chih-Hsun Lin

IPC: H01L21/336

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/32105

Abstract: The present invention relates to a method of forming an isolation structure, in which, a trench is formed in a substrate through a hard mask, and deposition, etch back, deposition, planarization, and etch back are performed in the order to form an isolation material layer of the isolation structure after the hard mask is removed. A silicon layer may be formed to cover the trench and original surface of the substrate before the former deposition, or to cover a part of the trench and original surface of the substrate after the former etch back and before the later deposition, to serve as a stop layer for the planarization process. Voids existing within the isolation material layer can be exposed or removed by partially etching the isolation material layer by the former etch back. The later deposition can be performed with a less aspect ratio to avoid forming voids.

Abstract translation: 本发明涉及一种形成隔离结构的方法，其中通过硬掩模在衬底中形成沟槽，并且进行沉积，回蚀刻，沉积，平坦化和回蚀以形成隔离 去除硬掩模后隔离结构的材料层。 可以形成硅层以在前一次沉积之前覆盖衬底的沟槽和原始表面，或者在前面的回蚀刻和稍后的沉积之前覆盖衬底的一部分沟槽和原始表面，以用作 停止层进行平面化处理。 存在于隔离材料层内的空隙可以通过由前面的回蚀部分蚀刻隔离材料层而被暴露或去除。 可以以较小的纵横比进行后续沉积以避免形成空隙。

公开(公告)号：US20200227269A1

公开(公告)日：2020-07-16

申请号：US16261578

申请日：2019-01-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Ta-Wei Chiu ,  Chia-Lung Chang ,  Po-Chun Chen ,  Hong-Yi Fang ,  Yi-Wei Chen

IPC: H01L21/3105 ,  H01L27/108 ,  H01L21/027 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.

公开(公告)号：US20200075397A1

公开(公告)日：2020-03-05

申请号：US16134982

申请日：2018-09-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Chun Chen ,  Hsuan-Tung Chu ,  Yi-Wei Chen ,  Wei-Hsin Liu ,  Yu-Cheng Tung ,  Chia-Lung Chang

IPC: H01L21/762 ,  H01L21/02

Abstract: A method of forming an isolation structure includes the following steps. A substrate having a first trench, a second trench and a third trench is provided, wherein the opening of the third trench is larger than the opening of the second trench, and the opening of the second trench is larger than the opening of the first trench. A first oxide layer is formed to conformally cover the first trench, the second trench and the third trench by an atomic layer deposition (ALD) process. A second oxide layer fills up the first trench by an in-situ steam generation (ISSG) process.

公开(公告)号：US20200020693A1

公开(公告)日：2020-01-16

申请号：US16583272

申请日：2019-09-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Po-Chun Chen ,  Chia-Lung Chang

IPC: H01L27/108 ,  H01L21/8234 ,  H01L21/02

Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.