公开(公告)号：US20230292498A1

公开(公告)日：2023-09-14

申请号：US18199346

申请日：2023-05-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Hsu-Yang Wang ,  Chun-Chieh Chiu ,  Shih-Fang Tzou

IPC: H10B12/00 ,  H01L21/768

CPC classification number: H10B12/485 ,  H01L21/76895 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76804 ,  H10B12/053 ,  H10B12/482

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

公开(公告)号：US20230238445A1

公开(公告)日：2023-07-27

申请号：US17676216

申请日：2022-02-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Chun-Chieh Chiu ,  Chun-Ling Lin ,  Shu Min Huang ,  Hsin-Fu Huang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L21/768 ,  H01L21/324

CPC classification number: H01L29/66431 ,  H01L29/2003 ,  H01L29/7786 ,  H01L21/76841 ,  H01L21/3245

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

公开(公告)号：US11711916B2

公开(公告)日：2023-07-25

申请号：US17161685

申请日：2021-01-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Hsu-Yang Wang ,  Chun-Chieh Chiu ,  Shih-Fang Tzou

IPC: H10B12/00 ,  H01L21/768

CPC classification number: H10B12/485 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76895 ,  H10B12/053 ,  H10B12/482

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

公开(公告)号：US20190341388A1

公开(公告)日：2019-11-07

申请号：US16001949

申请日：2018-06-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Hsu-Yang Wang ,  Chun-Chieh Chiu ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L21/768

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

公开(公告)号：US10276389B1

公开(公告)日：2019-04-30

申请号：US15987887

申请日：2018-05-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Yi-Wei Chen ,  Pin-Hong Chen ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chun-Chieh Chiu ,  Tsun-Min Cheng ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L27/108

Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a first metal silicon nitride layer on the silicon layer; performing an oxygen treatment process to form an oxide layer on the first metal silicon nitride layer; forming a second metal silicon nitride layer on the oxide layer; forming a conductive layer on the second metal silicon nitride layer; and patterning the conductive layer, the second metal silicon nitride layer, the oxide layer, the first metal silicon nitride layer, and the silicon layer to form a gate structure.

公开(公告)号：US10199269B2

公开(公告)日：2019-02-05

申请号：US15361503

申请日：2016-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Han Chen ,  Yen-Tsai Yi ,  Chun-Chieh Chiu ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Hsin-Fu Huang

IPC: H01L23/485 ,  H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78

Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.

公开(公告)号：US20180366368A1

公开(公告)日：2018-12-20

申请号：US15626168

申请日：2017-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Chieh Chiu ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Li-Han Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: The present invention provides a method for forming a contact structure, the method includes proving a substrate. An oxygen-containing dielectric layer is formed on the substrate. Next, a non-oxygen layer is formed on the oxygen-containing dielectric layer and a contact hole is then formed in the oxygen-containing dielectric layer. A metal layer is then formed in the contact hole and on the non-oxygen layer, with the non-oxygen layer disposed between the oxygen-containing dielectric layer and the metal layer. An anneal process is then performed to the metal layer, and a conductive layer is filled in the contact hole.

公开(公告)号：US10068797B2

公开(公告)日：2018-09-04

申请号：US15586240

申请日：2017-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

公开(公告)号：US09570348B2

公开(公告)日：2017-02-14

申请号：US14709083

申请日：2015-05-11

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu-Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

Abstract: A method of forming a contact structure is provided. A silicon-containing substrate is provided with a composite dielectric layer formed thereon. An opening penetrates through the composite dielectric layer and exposes a portion of the source/drain region. A titanium nitride layer is formed in the opening, and the titanium nitride layer is in contact with the exposed portion of the source/drain region. The titanium nitride layer is annealed, so that the bottom portion of the titanium nitride layer is partially transformed into a titanium silicide layer. A conductive layer is formed to fill up the opening.

Abstract translation: 提供一种形成接触结构的方法。 含硅基板上形成有复合电介质层。 开口穿过复合介电层并暴露出源/漏区的一部分。 在开口中形成氮化钛层，氮化钛层与源极/漏极区域的露出部分接触。 将氮化钛层退火，使得氮化钛层的底部部分转变为硅化钛层。 形成导电层以填充开口。

公开(公告)号：US10943909B2

公开(公告)日：2021-03-09

申请号：US16001949

申请日：2018-06-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Hsu-Yang Wang ,  Chun-Chieh Chiu ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L21/76 ,  H01L21/768

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.