公开(公告)号：US20230413690A1

公开(公告)日：2023-12-21

申请号：US18242550

申请日：2023-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Da-Jun Lin ,  Chih-Wei Chang ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/063 ,  H10B63/00 ,  H10N70/028 ,  H10N70/041 ,  H10N70/841 ,  H10N70/8833

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.

公开(公告)号：US20230260937A1

公开(公告)日：2023-08-17

申请号：US18138752

申请日：2023-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L2224/05124 ,  H01L2224/45147 ,  H01L2224/45464

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

公开(公告)号：US11723215B2

公开(公告)日：2023-08-08

申请号：US17106214

申请日：2020-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-An Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US20230157180A1

公开(公告)日：2023-05-18

申请号：US17548576

申请日：2021-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Chau-Chung Hou ,  Da-Jun Lin ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  H01L27/222 ,  G11C11/161 ,  H01L23/5226 ,  H01L21/7684

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a first inter-metal dielectric (IMD) layer on the MTJ, removing part of the first IMD layer to form a damaged layer on the MTJ and a trench exposing the damaged layer, performing a ultraviolet (UV) curing process on the damaged layer, and then conducting a planarizing process to remove the damaged layer and part of the first IMD layer.

公开(公告)号：US11632889B2

公开(公告)日：2023-04-18

申请号：US17375021

申请日：2021-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Chin-Chia Yang ,  Ting-An Chien

IPC: H10B63/00 ,  H10K10/50 ,  H10K10/82 ,  H10K19/00 ,  H10K71/20 ,  H10K85/20 ,  H10N70/20 ,  H10N70/00

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

公开(公告)号：US11605777B2

公开(公告)日：2023-03-14

申请号：US17006923

申请日：2020-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile stress pieces.

公开(公告)号：US20210408368A1

公开(公告)日：2021-12-30

申请号：US16916037

申请日：2020-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Shih-Wei Su ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.

公开(公告)号：US20210343789A1

公开(公告)日：2021-11-04

申请号：US17375021

申请日：2021-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Chin-Chia Yang ,  Ting-An Chien

IPC: H01L27/24 ,  H01L27/28 ,  H01L45/00 ,  H01L51/00 ,  H01L51/05 ,  H01L51/10

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

公开(公告)号：US20210074917A1

公开(公告)日：2021-03-11

申请号：US16589148

申请日：2019-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Ting-An Chien

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of forming a resistive random access memory cell includes the following steps. A first electrode layer, a blanket resistive switching material layer and a second electrode layer are formed on a layer sequentially. The second electrode layer is patterned to form a second electrode. The blanket resistive switching material layer is patterned to form a resistive switching material layer. An oxygen implanting process is performed to implant oxygen in two sidewall parts of the resistive switching material layer.

公开(公告)号：US20200266095A1

公开(公告)日：2020-08-20

申请号：US16866360

申请日：2020-05-04

Applicant: United Microelectronics Corp.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Chich-Neng Chang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.