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    Structure of a nonvolatile memory device with a low-voltage transistor fabricated on a substrate
    21.
    发明授权
    Structure of a nonvolatile memory device with a low-voltage transistor fabricated on a substrate 有权

    公开(公告)号：US11100995B2

    公开(公告)日：2021-08-24

    申请号：US17030124

    申请日：2020-09-23

    Applicant: United Microelectronics Corp.

    Inventor： Liang Yi ,  Zhaobing Li ,  Chi Ren

    IPC: G11C16/04 ,  H01L45/00 ,  G11C13/00 ,  H01L27/11517

    Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

    Structure of memory device having floating gate with protruding structure
    22.
    发明授权
    Structure of memory device having floating gate with protruding structure 有权

    公开(公告)号：US11056495B2

    公开(公告)日：2021-07-06

    申请号：US16455297

    申请日：2019-06-27

    Applicant: United Microelectronics Corp.

    Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

    IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/51 ,  H01L29/423

    Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate.

    Semiconductor structure and method for forming the same
    23.
    发明授权
    Semiconductor structure and method for forming the same 有权

    公开(公告)号：US10153359B2

    公开(公告)日：2018-12-11

    申请号：US15234525

    申请日：2016-08-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Liang Yi ,  Shen-De Wang

    IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11546

    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least a second cell. The substrate has a first region and a second region. The first and second cells are in the first and second regions respectively. The first cell comprises a first dielectric layer, a floating gate electrode, an oxide-nitride-oxide (ONO) gate dielectric layer, a second dielectric layer, and a control gate electrode. The ONO gate dielectric layer is on the floating gate electrode in the first dielectric layer on the substrate. The control gate electrode is in both of the first dielectric layer and the second dielectric layer on the first dielectric layer. The ONO gate dielectric layer contacting with the control gate electrode is wholly below a top surface of the first dielectric layer.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    25.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20180033961A1

    公开(公告)日：2018-02-01

    申请号：US15260754

    申请日：2016-09-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Liang Yi ,  Chia-Ching Hsu ,  Shen-De Wang ,  Ko-Chi Chen

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (ReRAM) cell structure, and an upper metal layer. The bottom metal layer is located above the substrate. The ReRAM cell structure is formed on the bottom metal layer. The ReRAM cell structure includes a bottom electrode, a memory cell layer, a top electrode, and a spacer. The memory cell layer is formed on the bottom electrode. The top electrode is formed on the memory cell layer. The spacer is formed on two sides of the bottom electrode, the memory cell layer and the top electrode. The upper metal layer is electrically connected to and directly contacting the top electrode.

    Split gate non-volatile memory device and method for fabricating the same
    27.
    发明授权
    Split gate non-volatile memory device and method for fabricating the same 有权
    分闸非易失性存储器件及其制造方法

    公开(公告)号：US09379128B1

    公开(公告)日：2016-06-28

    申请号：US14809342

    申请日：2015-07-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Liang Yi ,  Ko-Chi Chen ,  Shen-De Wang ,  Chia-Ching Hsu ,  Chun-Sung Huang ,  Wen-Peng Hsu

    IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28 ,  H01L21/225

    CPC classification number: H01L27/11568 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

    Abstract: A split gate NVM device includes a semiconductor substrate, an ONO structure disposed on the semiconductor substrate, a first gate electrode disposed on the ONO structure, a second gate electrode disposed on the semiconductor substrate, adjacent to and insulated from the first gate electrode and the ONO structure, a first doping region with a first conductivity formed in the semiconductor substrate and adjacent to the ONO structure, a second doping region with the first conductivity formed in the semiconductor substrate and adjacent to the second gate electrode, and a third doping region with the first conductivity formed in the semiconductor substrate, disposed between the first doping region and the second doping region and adjacent to the ONO structure and the second gate electrode.

    Abstract translation: 分路门NVM器件包括半导体衬底，设置在半导体衬底上的ONO结构，设置在ONO结构上的第一栅电极，设置在半导体衬底上的第二栅极，与第一栅电极相邻并绝缘， ONO结构，在半导体衬底中形成并与ONO结构相邻的具有第一导电性的第一掺杂区，在半导体衬底中形成并与第二栅电极相邻的具有第一导电性的第二掺杂区，以及第三掺杂区， 所述第一导电体形成在所述半导体衬底中，设置在所述第一掺杂区域和所述第二掺杂区域之间并且邻近所述ONO结构和所述第二栅电极。

    Semiconductor memory device and fabrication method thereof
    29.
    发明授权
    Semiconductor memory device and fabrication method thereof 有权

    公开(公告)号：US12040369B2

    公开(公告)日：2024-07-16

    申请号：US17835965

    申请日：2022-06-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Liang Yi ,  Chi Ren

    IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

    CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

    Abstract: A semiconductor memory device includes a substrate, a pair of floating gates disposed on the substrate, a source line doped region in the substrate between the floating gates, an erase gate disposed between the floating gates and on the source line doped region, a word line disposed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate, and a bit line doped region in the substrate and adjacent to the word line. An upper surface of the source line doped region has a concave profile lower than a surface of the substrate and with a radius between 40 nm and 60 nm in a cross-sectional view perpendicular to the floating gates.

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