公开(公告)号：US12185532B2

公开(公告)日：2024-12-31

申请号：US18365243

申请日：2023-08-04

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H10B41/30 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788

Abstract: A structure of memory device includes an active region in a substrate, a dielectric layer on the active region, and a floating gate disposed on the dielectric layer. The active region extends along a first direction in a top-view. The floating gate includes a first protruding structure extending along the first direction from a sidewall of the floating gate protruding from a top surface of the substrate. The whole of the first protruding structure is located in the active region.

公开(公告)号：US11765893B2

公开(公告)日：2023-09-19

申请号：US17331319

申请日：2021-05-26

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H10B41/30 ,  H01L29/788 ,  H01L29/51 ,  H01L29/423

CPC classification number: H10B41/30 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/518 ,  H01L29/788

Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate, and crosses over the trench isolation lines.

公开(公告)号：US20210280590A1

公开(公告)日：2021-09-09

申请号：US17331319

申请日：2021-05-26

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/51 ,  H01L29/423

Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate, and crosses over the trench isolation lines.

公开(公告)号：US11056495B2

公开(公告)日：2021-07-06

申请号：US16455297

申请日：2019-06-27

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/51 ,  H01L29/423

Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate.

公开(公告)号：US20240355936A1

公开(公告)日：2024-10-24

申请号：US18327081

申请日：2023-06-01

Applicant: United Microelectronics Corp.

Inventor： Boon Keat Toh ,  Chih-Hsin Chang ,  Szu Han Wu ,  Chi Ren

IPC: H01L29/788 ,  H01L29/45 ,  H01L29/66 ,  H10B41/35

CPC classification number: H01L29/788 ,  H01L29/456 ,  H01L29/66492 ,  H01L29/66825 ,  H10B41/35

Abstract: Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate having a first memory region. The first memory region includes a first dielectric layer, a first floating gate, a first inter-gate dielectric layer, a control gate and a first contact. The first dielectric layer is disposed on the substrate. The first floating gate is disposed on the first dielectric layer. The first inter-gate dielectric layer is disposed on the first floating layer. The control gate is disposed on the first inter-gate dielectric layer. The first contact penetrates through the first control gate and the first inter-gate dielectric layer and is landed on the first floating gate.

公开(公告)号：US11943920B2

公开(公告)日：2024-03-26

申请号：US17468637

申请日：2021-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Xiaojuan Gao ,  Boon Keat Toh

IPC: H01L27/11531 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B41/42 ,  H10B43/40

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H10B43/40

Abstract: A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.

公开(公告)号：US20230380154A1

公开(公告)日：2023-11-23

申请号：US18365243

申请日：2023-08-04

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H10B41/30 ,  H01L29/788 ,  H01L29/51 ,  H01L29/423

CPC classification number: H10B41/30 ,  H01L29/788 ,  H01L29/518 ,  H01L29/513 ,  H01L29/42328

Abstract: A structure of memory device includes an active region in a substrate, a dielectric layer on the active region, and a floating gate disposed on the dielectric layer. The active region extends along a first direction in a top-view. The floating gate includes a first protruding structure extending along the first direction from a sidewall of the floating gate protruding from a top surface of the substrate. The whole of the first protruding structure is located in the active region.

公开(公告)号：US20230045722A1

公开(公告)日：2023-02-09

申请号：US17468637

申请日：2021-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Xiaojuan Gao ,  Boon Keat Toh

IPC: H01L27/11531 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.