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公开(公告)号：US20240237549A1
公开(公告)日：2024-07-11
申请号：US18610212
申请日：2024-03-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jin-Yan Chiou , Wei-Chuan Tsai , Hsin-Fu Huang , Yen-Tsai Yi , Hsiang-Wen Ke
CPC classification number: H10N50/80 , G11C11/161 , H10N50/01 , H01F10/3254 , H01F41/32 , H10N50/85
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.
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公开(公告)号：US11968906B2
公开(公告)日：2024-04-23
申请号：US16882552
申请日：2020-05-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jin-Yan Chiou , Wei-Chuan Tsai , Hsin-Fu Huang , Yen-Tsai Yi , Hsiang-Wen Ke
CPC classification number: H10N50/80 , G11C11/161 , H10N50/01 , H01F10/3254 , H01F41/32 , H10N50/85
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.
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公开(公告)号：US20230387280A1
公开(公告)日：2023-11-30
申请号：US17851048
申请日：2022-06-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yen-Tsai Yi , Wei-Chuan Tsai , Jin-Yan Chiou , Hsiang-Wen Ke
IPC: H01L29/778 , H01L29/20 , H01L29/08 , H01L29/66
CPC classification number: H01L29/7783 , H01L29/2003 , H01L29/0847 , H01L29/66462
Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a titanium nitride (TiN) layer on the p-type semiconductor layer as a nitrogen to titanium (N/Ti) ratio of the TiN layer is greater than 1, forming a passivation layer on the TiN layer and the barrier layer, removing the passivation layer to form an opening, forming a gate electrode in the opening, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode on the buffer layer.
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公开(公告)号：US10756128B2
公开(公告)日：2020-08-25
申请号：US16244109
申请日：2019-01-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuo-Chih Lai , Shih-Min Chou , Ko-Wei Lin , Chin-Fu Lin , Wei-Chuan Tsai , Chun-Yao Yang , Chia-Fu Cheng , Yi-Syun Chou , Wei Chen
IPC: H01L27/14 , H01L27/146 , H01L21/768 , H01L49/02
Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.
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公开(公告)号：US20200212090A1
公开(公告)日：2020-07-02
申请号：US16244109
申请日：2019-01-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuo-Chih Lai , Shih-Min Chou , Ko-Wei Lin , Chin-Fu Lin , Wei-Chuan Tsai , Chun-Yao Yang , Chia-Fu Cheng , Yi-Syun Chou , Wei Chen
IPC: H01L27/146 , H01L49/02 , H01L21/768
Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.
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Patent Agency Ranking
公开(公告)号：US10134629B1
公开(公告)日：2018-11-20
申请号：US15696267
申请日：2017-09-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Yen-Tsai Yi , Wei-Chuan Tsai , En-Chiuan Liou , Chih-Wei Yang
IPC: H01L21/44 , H01L21/768 , H01L29/78 , H01L23/532 , H01L23/535
Abstract: A method for manufacturing a semiconductor structure includes the following steps. At first, a titanium layer is formed on a preformed layer. Then, a first titanium nitride layer is formed on the titanium layer. A first plasma treatment is applied to the first titanium nitride layer such that the first titanium nitride layer has a first N/Ti ratio. A second titanium nitride layer is formed on the first titanium nitride layer. A second plasma treatment is applied to the second titanium nitride layer such that the second titanium nitride layer has a second N/Ti ratio larger than the first N/Ti ratio.
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公开(公告)号：US09755047B2
公开(公告)日：2017-09-05
申请号：US14924532
申请日：2015-10-27
Applicant: United Microelectronics Corp.
Inventor： Pin-Hong Chen , Kuo-Chih Lai , Chia-Chang Hsu , Chun-Chieh Chiu , Li-Han Chen , Min-Chuan Tsai , Kuo-Chin Hung , Wei-Chuan Tsai , Hsin-Fu Huang , Chi-Mao Hsu
IPC: H01L27/088 , H01L29/66 , H01L29/78 , H01L21/285
CPC classification number: H01L29/665 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L29/267 , H01L29/45 , H01L29/7845 , H01L29/785
Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
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公开(公告)号：US12183801B2
公开(公告)日：2024-12-31
申请号：US17510394
申请日：2021-10-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jin-Yan Chiou , Wei-Chuan Tsai , Yen-Tsai Yi , Hsiang-Wen Ke
Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.
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公开(公告)号：US12089504B2
公开(公告)日：2024-09-10
申请号：US17361331
申请日：2021-06-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yen-Tsai Yi , Wei-Chuan Tsai , Jin-Yan Chiou , Hsiang-Wen Ke
Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming a first top electrode on the MTJ stack, and then forming a second top electrode on the first top electrode. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.
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公开(公告)号：US20240237550A1
公开(公告)日：2024-07-11
申请号：US18611753
申请日：2024-03-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jin-Yan Chiou , Wei-Chuan Tsai , Hsin-Fu Huang , Yen-Tsai Yi , Hsiang-Wen Ke
CPC classification number: H10N50/80 , G11C11/161 , H10N50/01 , H01F10/3254 , H01F41/32 , H10N50/85
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a
MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.
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