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公开(公告)号：US10811272B2
公开(公告)日：2020-10-20
申请号：US16261578
申请日：2019-01-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Hsin Liu , Ta-Wei Chiu , Chia-Lung Chang , Po-Chun Chen , Hong-Yi Fang , Yi-Wei Chen
IPC: H01L21/3105 , H01L21/027 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L27/108 , H01L29/66
Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
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公开(公告)号：US20190280095A1
公开(公告)日：2019-09-12
申请号：US15943717
申请日：2018-04-03
Inventor： Po-Chun Chen , Chia-Lung Chang , Yi-Wei Chen , Wei-Hsin Liu , Han-Yung Tsai
IPC: H01L29/423 , H01L21/762 , H01L27/108 , H01L21/28
Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
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公开(公告)号：US10340278B1
公开(公告)日：2019-07-02
申请号：US15885729
申请日：2018-01-31
Inventor： Wei-Hsin Liu , Cheng-Hsu Huang , Jui-Min Lee , Yi-Wei Chen
IPC: H01L23/48 , H01L27/108 , H01L23/528 , H01L21/3205 , H01L21/768 , H01L21/285 , H01L23/532
CPC classification number: H01L27/10894 , H01L21/28556 , H01L21/32053 , H01L21/32055 , H01L21/7685 , H01L21/76856 , H01L21/76864 , H01L21/76879 , H01L23/528 , H01L23/53266 , H01L23/53271 , H01L23/5329 , H01L27/10823 , H01L27/10885 , H01L27/10888 , H01L27/10897
Abstract: A semiconductor memory device includes a semiconductor substrate and a patterned conductive structure. The patterned conductive structure is disposed on the semiconductor substrate. The patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer. The second silicon conductive layer is disposed on the first silicon conductive layer. The interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen. The barrier layer is disposed on the second silicon conductive layer. The metal conductive layer is disposed on the barrier layer.
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公开(公告)号：US10276650B2
公开(公告)日：2019-04-30
申请号：US15927103
申请日：2018-03-21
Inventor： Tzu-Chin Wu , Wei-Hsin Liu , Yi-Wei Chen , Chia-Lung Chang , Jui-Min Lee , Po-Chun Chen , Li-Wei Feng , Ying-Chiao Wang , Wen-Chieh Lu , Chien-Ting Ho , Tsung-Ying Tsai , Kai-Ping Chen
IPC: H01L27/108 , H01L49/02 , H01L29/94
Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
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公开(公告)号：US10186453B2
公开(公告)日：2019-01-22
申请号：US14738943
申请日：2015-06-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Hsin Liu , Bin-Siang Tsai
IPC: H01L21/768 , H01L23/522 , H01L21/02 , H01L21/311 , H01L21/32 , H01L23/532 , H01L21/3105 , H01L23/485
Abstract: A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal patterns and the first dielectric layer. A modification process is performed to modify a part of the modifiable layer on top sides of the metal patterns, thereby top masks being formed. A removing process is performed to remove a part of the modifiable layer on sidewalls of the metal patterns but preserve the top masks. A dielectric layer having voids under the top masks and between the metal patterns is formed. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.
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Patent Agency Ranking
26.发明申请公开(公告)号：US20180190662A1
公开(公告)日：2018-07-05
申请号：US15854825
申请日：2017-12-27
Inventor： Tzu-Chin Wu , Wei-Hsin Liu , Yi-Wei Chen , Mei-Ling Chen , Chia-Lung Chang , Ching-Hsiang Chang , Jui-Min Lee , Tsun-Min Cheng , Lin-Chen Lu , Shih-Fang Tzou , Kai-Jiun Chang , Chih-Chieh Tsai , Tzu-Chieh Chen , Chia-Chen Wu
IPC: H01L27/108 , H01L21/033 , H01L23/532 , H01L23/528 , H01L21/768 , H01L21/285
CPC classification number: H01L27/10885 , H01L21/0332 , H01L21/0337 , H01L21/28568 , H01L21/32139 , H01L21/76846 , H01L21/76877 , H01L23/528 , H01L23/53266 , H01L23/53271 , H01L27/10823 , H01L27/10876
Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following. A hard mask layer is formed on a metal stack by a chemical vapor deposition process importing nitrogen (N2) gases and then importing amonia (NH3) gases. The present invention also provides a bit line gate structure of a dynamic random access memory (DRAM) including a metal stack and a hard mask. The metal stack includes a polysilicon layer, a titanium layer, a titanium nitride layer, a first tungsten nitride layer, a tungsten layer and a second tungsten nitride layer stacked from bottom to top. The hard mask is disposed on the metal stack.
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27.发明申请公开(公告)号：US20170345819A1
公开(公告)日：2017-11-30
申请号：US15681570
申请日：2017-08-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Hsin Liu , Pi-Hsuan Lai
IPC: H01L27/088 , H01L21/033 , H01L27/02 , H01L21/8234 , H01L27/11
CPC classification number: H01L27/088 , H01L21/0332 , H01L21/823456 , H01L27/0207 , H01L27/1104 , H01L27/1116
Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.
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公开(公告)号：US09589846B1
公开(公告)日：2017-03-07
申请号：US15006053
申请日：2016-01-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Fu-Yu Tsai , Wei-Hsin Liu , Han-Sheng Huang
IPC: H01L21/82 , H01L21/8234 , H01L29/66
CPC classification number: H01L21/823462 , H01L29/4966 , H01L29/66545 , H01L29/7833
Abstract: A method for forming a semiconductor device is provided. First, a dielectric layer is provided on a substrate, wherein a first recess and a second recess are formed in the dielectric layer. After a mask layer is filled into the first recess and the second recess, the mask layer in the second recess is removed away, thereby forming a patterned mask layer. Subsequently, a nitride treatment is performed to remove unwanted residue of the mask layer in the second recess.
Abstract translation: 提供一种形成半导体器件的方法。 首先，在基板上设置电介质层，其中在电介质层中形成有第一凹部和第二凹部。 在将掩模层填充到第一凹部和第二凹部中之后，将第二凹部中的掩模层去除，从而形成图案化掩模层。 随后，进行氮化处理以去除第二凹陷中的掩模层的不需要的残留物。
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公开(公告)号：US11088023B2
公开(公告)日：2021-08-10
申请号：US15927106
申请日：2018-03-21
Inventor： Pin-Hong Chen , Chih-Chieh Tsai , Tzu-Chieh Chen , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Tsun-Min Cheng , Yi-Wei Chen , Wei-Hsin Liu
IPC: H01L21/768 , H01L21/324 , H01L27/108 , H01L23/532 , H01L21/285
Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.
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公开(公告)号：US20200227269A1
公开(公告)日：2020-07-16
申请号：US16261578
申请日：2019-01-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Hsin Liu , Ta-Wei Chiu , Chia-Lung Chang , Po-Chun Chen , Hong-Yi Fang , Yi-Wei Chen
IPC: H01L21/3105 , H01L27/108 , H01L21/027 , H01L29/66 , H01L21/311 , H01L21/3213 , H01L21/02
Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
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