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公开(公告)号：US20180053483A1
公开(公告)日：2018-02-22
申请号：US15802951
申请日：2017-11-03
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
发明人： Juncheng XIAO , Mang ZHAO
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2310/0251 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2330/04
摘要： A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.
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公开(公告)号：US20180053481A1
公开(公告)日：2018-02-22
申请号：US15802865
申请日：2017-11-03
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
发明人： Juncheng XIAO , Mang ZHAO
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2310/0251 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2330/04
摘要： A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.
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公开(公告)号：US20170193956A1
公开(公告)日：2017-07-06
申请号：US14891646
申请日：2015-10-21
申请人： Shenzhen china Star Optoelectronics Technology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
发明人： Juncheng XIAO , Mang ZHAO
IPC分类号： G09G3/36 , G02F1/1362 , G02F1/1368 , G02F1/1335
CPC分类号： G09G3/3696 , G02F1/133514 , G02F1/136204 , G02F1/1368 , G02F2202/22 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/04 , G11C19/184
摘要： The invention disclosure a GOA circuit and a liquid crystal display. The GOA circuit including an electrical potential pull-down controlling circuit and a plurality of GOA sub circuits in cascade connection, the electrical potential pull-down controlling circuit comprising a first voltage limited transistor, a second filter transistor and a third transistor. The first voltage limited transistor, and the second filter transistor a reconnected in series and between the output terminal of the initial scanning signal, STV signal and the control terminal of the third transistor, the control terminal of the first voltage limited transistor and the first terminal of the third transistor is connected to the first power terminal and the second terminal of the third transistor is connected to the GOA sub circuit. By this design, the damage from the large static electricity to the GOA sub circuit can be avoided.
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公开(公告)号：US20170186878A1
公开(公告)日：2017-06-29
申请号：US14890698
申请日：2015-10-21
申请人： Shenzhen China Star Optoelectronics Technology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
发明人： Juncheng XIAO , Mang ZHAO
IPC分类号： H01L29/786 , H01L25/065 , G03F1/22 , H01L29/417
CPC分类号： H01L29/78621 , G03F1/22 , H01L25/0655 , H01L29/41733 , H01L29/66765 , H01L29/78624 , H01L29/78678 , H01L29/78696
摘要： The disclosure provides a manufacturing method for TFT array substrate, a TFT array substrate and a display device. The manufacturing method includes following steps: in sequence, forming a gate pattern layer, a gate insulating layer, a patterned poly-silicon layer, a separation layer on s substrate, and adopting a mask to form a source pattern layer and a drain pattern layer on the separation layer by photolithography processes. The source pattern layer and the drain pattern layer are connected to the patterned poly-silicon layer. The mask blocks one side of the channel area, and the same mask is adopted to form a lightly doped area on the other side of the channel area not blocked by the mask. The disclosure may reduce production costs and has great design flexibility.
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公开(公告)号：US20170033127A1
公开(公告)日：2017-02-02
申请号：US14783870
申请日：2015-08-21
IPC分类号： H01L27/12 , H03K5/135 , H01L27/092 , H03K17/687 , H01L29/786 , H01L29/417
CPC分类号： H01L27/1222 , H01L27/092 , H01L27/1225 , H01L27/124 , H01L27/1248 , H01L29/41733 , H01L29/78603 , H01L29/78606 , H01L29/78633 , H01L29/78648 , H01L29/78675 , H03K5/135
摘要： A control circuit of a thin film transistor, comprising: a substrate; a silicon nitride layer disposed on the substrate; a silicon dioxide layer disposed on the silicon nitride layer; a light shielding layer disposed inside the silicon nitride layer, which comprising a first light shielding region and a second light shielding region; at least one N type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the first light shielding region; at least one P type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the second light shielding region; each of the N type metal oxide semiconductor and the P type metal oxide semiconductor has a gate electrode layer, a first control signal received by voltage pulses of the gate electrode layer synchronized with a second control signal received by the light shielding layer in voltage variation.
摘要翻译： 1.一种薄膜晶体管的控制电路，包括：基板; 设置在所述基板上的氮化硅层; 设置在氮化硅层上的二氧化硅层; 设置在所述氮化硅层内部的遮光层，其包括第一遮光区域和第二遮光区域; 在与所述第一遮光区域对应的位置配置在所述二氧化硅层上的至少一个N型金属氧化物半导体; 在与所述第二遮光区域对应的位置配置在所述二氧化硅层上的至少一个P型金属氧化物半导体; N型金属氧化物半导体和P型金属氧化物半导体中的每一个具有栅电极层，通过栅电极层的电压脉冲接收的第一控制信号与由遮光层接收的电压变化的第二控制信号同步。
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公开(公告)号：US20230176435A1
公开(公告)日：2023-06-08
申请号：US16966106
申请日：2020-06-19
发明人： Yanyang LI , Mang ZHAO , Yong TIAN
IPC分类号： G02F1/1368 , H01L27/12 , G02F1/1333 , G02F1/1362 , G02F1/1335 , G06F3/041
CPC分类号： G02F1/1368 , G02F1/13338 , G02F1/133514 , G02F1/136286 , G06F3/0412 , G06F3/04164 , H01L27/124
摘要： A thin film transistor array substrate and a touch display panel are provided, including a plurality of touch electrodes. The touch electrodes include a first touch electrode, a second touch electrode, and a third touch electrode arranged along a first direction. A number of the touch traces electrically connected between the second touch electrode and the first common power line is greater than or equal to a number of the touch traces electrically connected between the first touch electrode and the first common power line, and is less than a number of the touch traces electrically connected between the third touch electrode and the first common power line.
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公开(公告)号：US20220187954A1
公开(公告)日：2022-06-16
申请号：US17260154
申请日：2020-06-17
发明人： Mang ZHAO , Yanyang LI , Yong TIAN
IPC分类号： G06F3/044 , G06F3/041 , G02F1/1368 , G02F1/1333 , G02F1/1343 , G02F1/1362
摘要： The present application provides a thin film transistor array substrate and a touch display panel including a plurality of touch electrodes, and the touch electrodes including a first touch electrode, a second touch electrode, and a third touch electrode arranged in a first direction. A number of touch trace electrically connected to the second touch electrode and the driver chip is greater than or equal to a number of touch trace electrically connected to the first touch electrode and the driver chip, and is less than a number of touch trace electrically connected to the third touch electrode and the driver chip.
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公开(公告)号：US20200251034A1
公开(公告)日：2020-08-06
申请号：US16335249
申请日：2018-12-19
发明人： Lihua ZHENG , Mang ZHAO , Yong TIAN
IPC分类号： G09G3/20
摘要： According to a drive method for the display panel, m multiplex signals sequentially generate the high level pulse at the beginning of the (2i−1)th row period in a predetermined order. The high level pulse of the multiplex signal that is the last one to generate the high level pulse in the (2i−1)th row period continues until the end of the (2i−1)th row period. The m multiplex signals sequentially generate the high level pulse at the beginning of the (2i)th row period in a reverse order to the predetermined order. The high level pulse of the multiplex signal that is the last one to generate the high level pulse in the (2i)th row period continues until the end of the 2i row period. As a result, the number of times that the levels of the multiplex signals are changed in a frame period can be decreased to reduce the power consumption.
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公开(公告)号：US20200168158A1
公开(公告)日：2020-05-28
申请号：US16332357
申请日：2018-12-21
发明人： Lihua ZHENG , Mang ZHAO , Yong TIAN
IPC分类号： G09G3/3266 , G09G3/36
摘要： A drive method for a display panel is provided. A first multiplex signal, a second multiplex signal, a third multiplex signal, a fourth multiplex signal, a fifth multiplex signal, and a sixth multiplex signal sequentially generate the high level pulse in the predetermined order in each of the first row periods of the (2i−1)th multiplex period. In addition, the first multiplex signal, the second multiplex signal, the third multiplex signal, the fourth multiplex signal, the fifth multiplex signal, and the sixth multiplex signal sequentially generate the high level pulse in a reverse order to the predetermined order in each of the second row periods of the (2i)th multiplex period. As a result, mura within the display picture of the display panel is eliminated to improve the display quality.
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公开(公告)号：US20180190200A1
公开(公告)日：2018-07-05
申请号：US14863610
申请日：2015-08-10
申请人： SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. , WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Juncheng XIAO , Mang ZHAO , Yong TIAN
IPC分类号： G09G3/3266 , G09G3/3233
CPC分类号： G09G3/3266 , G09G3/3233 , G09G3/36 , G09G3/3674 , G09G3/3677 , G09G2310/0286 , H01L21/822 , H01L27/1225 , H01L27/1251
摘要： The present invention provides a scan driving circuit utilized to drive cascading scan lines. The scan driving circuit comprises a pull-down control module, a pull-down module, a reset control module, a reset module, a lower transmission module, a first bootstrap capacitor, a constant low voltage source, and a constant high voltage source. By use of the deployment of the reset module, the scan driving circuit of the present invention improves the stability of the scan driving circuit and meanwhile, the structure of the whole scan driving circuit is simplified.
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