公开(公告)号：US20070120056A1

公开(公告)日：2007-05-31

申请号：US11599343

申请日：2006-11-15

申请人： Wataru Nagatomo ,  Atsushi Miyamoto ,  Ryoichi Matsuoka

发明人： Wataru Nagatomo ,  Atsushi Miyamoto ,  Ryoichi Matsuoka

IPC分类号： G21K7/00

CPC分类号： H01J37/28 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/70525 ,  G03F7/70625 ,  G06T7/0006 ,  G06T2207/30148 ,  H01J37/222 ,  H01J37/265 ,  H01J37/3174 ,  H01J2237/216 ,  H01J2237/24578 ,  H01J2237/2487 ,  H01J2237/2817

摘要： The present invention provides a semiconductor pattern shape evaluating apparatus using a critical dimension SEM, which eliminates the necessity of data conversion corresponding to each process of semiconductor manufacturing conventionally required; controls possessed data integratedly; can select data effective for use in each process from the possessed data easily; if the shape of formed pattern changes with time, can create a photographing recipe which enables stable measurement by correcting the photographing recipe based on time-series data. Specifically, the semiconductor pattern shape evaluating apparatus correlates coordinate systems among diversified data to control the diversified data stored in a database integratedly, selects part or all of the diversified data arbitrarily and creates a photographing recipe for observing a semiconductor pattern with a critical dimension SEM using selected data.

摘要翻译： 本发明提供一种使用临界尺寸SEM的半导体图案形状评估装置，其消除了对应于常规所需的半导体制造的每个处理的数据转换的必要性; 控制统计数据; 可以轻松地从拥有的数据中选择有效用于每个进程的数据; 如果形成的图案的形状随着时间而变化，则可以创建通过基于时间序列数据校正摄影配方而能够进行稳定测量的拍摄配方。 具体地，半导体图案形状评估装置将多个数据中的坐标系统相互关联，以一体化地存储在数据库中控制多样化数据，任意地选择部分或全部多样化数据，并使用临界尺寸SEM创建用于观察半导体图案的拍摄配方 选择的数据。

公开(公告)号：US07615746B2

公开(公告)日：2009-11-10

申请号：US11599343

申请日：2006-11-15

申请人： Wataru Nagatomo ,  Atsushi Miyamoto ,  Ryoichi Matsuoka

发明人： Wataru Nagatomo ,  Atsushi Miyamoto ,  Ryoichi Matsuoka

IPC分类号： G01N23/00 ,  G01B11/14

CPC分类号： H01J37/28 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/70525 ,  G03F7/70625 ,  G06T7/0006 ,  G06T2207/30148 ,  H01J37/222 ,  H01J37/265 ,  H01J37/3174 ,  H01J2237/216 ,  H01J2237/24578 ,  H01J2237/2487 ,  H01J2237/2817

摘要： The present invention provides a semiconductor pattern shape evaluating apparatus using a critical dimension SEM, which eliminates the necessity of data conversion corresponding to each process of semiconductor manufacturing conventionally required; controls possessed data integratedly; can select data effective for use in each process from the possessed data easily; if the shape of formed pattern changes with time, can create a photographing recipe which enables stable measurement by correcting the photographing recipe based on time-series data. Specifically, the semiconductor pattern shape evaluating apparatus correlates coordinate systems among diversified data to control the diversified data stored in a database integratedly, selects part or all of the diversified data arbitrarily and creates a photographing recipe for observing a semiconductor pattern with a critical dimension SEM using selected data.

摘要翻译： 本发明提供一种使用临界尺寸SEM的半导体图案形状评估装置，其消除了对应于常规所需的半导体制造的每个处理的数据转换的必要性; 控制统计数据; 可以轻松地从拥有的数据中选择有效用于每个进程的数据; 如果形成的图案的形状随着时间而变化，则可以创建通过基于时间序列数据校正摄影配方而能够进行稳定测量的拍摄配方。 具体地，半导体图案形状评估装置将多个数据中的坐标系统相互关联，以一体化地存储在数据库中控制多样化数据，任意地选择部分或全部多样化数据，并使用临界尺寸SEM创建用于观察半导体图案的拍摄配方 选择的数据。

公开(公告)号：US20090212215A1

公开(公告)日：2009-08-27

申请号：US12369774

申请日：2009-02-12

申请人： Wataru Nagatomo ,  Chie Shishido ,  Maki Tanaka

发明人： Wataru Nagatomo ,  Chie Shishido ,  Maki Tanaka

IPC分类号： G01N23/00

CPC分类号： G01N23/225

摘要： In dimension measurement of semiconductor pattern by CD-SEM, the error value between dimensional measurement value and actual dimension on the pattern is much variational as it is dependent on the cross-sectional shape of the pattern, and a low level of accuracy was one time a big problem. In the present invention, a plurality of patterns, each different in shape, were prepared beforehand with AFM measurement result and patterns of the same shape measured by CD-SEM. These measurement results and dimensional errors were homologized with each other and kept in a database. For actual measurement of dimensions, most like side wall shape, and corresponding CD-SEM measurement error result are called up, and the called-up error results are used to correct CD-SME results of measurement object patterns. In this manner, it becomes possible to correct or reduce dimensional error which is dependent on cross-sectional shape of the pattern.

摘要翻译： 通过CD-SEM对半导体图案的尺寸测量，尺寸测量值与图案上的实际尺寸之间的误差值是很大的变化，因为它取决于图案的截面形状，并且低水平的精度是一次 一个大问题。 在本发明中，通过AFM测定结果和通过CD-SEM测定的相同形状的图案，预先制作各种不同形状的图案。 将这些测量结果和尺寸误差彼此同源化并保存在数据库中。 对于尺寸的实际测量，调用大多数侧壁形状和相应的CD-SEM测量误差结果，并使用调用误差结果来校正测量对象图案的CD-SME结果。 以这种方式，可以校正或减小取决于图案的横截面形状的尺寸误差。

公开(公告)号：US10535129B2

公开(公告)日：2020-01-14

申请号：US13981963

申请日：2011-12-07

申请人： Masahiro Kitazawa ,  Mitsuji Ikeda ,  Yuichi Abe ,  Junichi Taguchi ,  Wataru Nagatomo

发明人： Masahiro Kitazawa ,  Mitsuji Ikeda ,  Yuichi Abe ,  Junichi Taguchi ,  Wataru Nagatomo

IPC分类号： G06T7/00

摘要： It is an object of the present invention to provide a semiconductor inspection apparatus capable of well carrying out position alignment and correctly determining whether the position alignment has been carried out successfully or has ended in a failure without operator interventions even if an inspected image is an image having few characteristics as is the case with a repetitive pattern or the inspected image is an image having a complicated shape.The semiconductor inspection apparatus includes means for imaging a shape on a wafer or on an exposure mask; means for storing an image inspected by the imaging means; means for storing design data of the semiconductor circuit corresponding to a position on the wafer or on the exposure mask which are to be imaged by the imaging means; means for storing a design-data image obtained as a result of converting the design data into an image; means for generating a design-data ROI image by converting an interest drawing region found from a relative crude-density relation of a shape included in the design-data image into an image; and a position alignment section configured to carry out position alignment on the inspected image and the design-data image. The semiconductor inspection apparatus makes use of the design-data ROI image in order to identify a position at which the inspected image and the design-data image match each other or compute the degree of coincidence.

公开(公告)号：US08214166B2

公开(公告)日：2012-07-03

申请号：US12137779

申请日：2008-06-12

申请人： Maki Tanaka ,  Wataru Nagatomo

发明人： Maki Tanaka ,  Wataru Nagatomo

IPC分类号： G01P21/00

CPC分类号： H01J37/263 ,  H01J37/222 ,  H01J2237/221 ,  H01J2237/24578 ,  H01J2237/24592 ,  H01J2237/2815 ,  H01J2237/2816 ,  H01J2237/2817 ,  H01J2237/2823 ,  H01J2237/2826

摘要： A method, and a corresponding system, are provided for calibrating data of an object measured by different measuring tools, including measuring a Critical-Dimension (CD) and roughness of an object by using a CD-SEM tool, calculating a number of cross section measurement points required for calibration, by statistically processing the roughness of the object, measuring the cross section of the object by using a cross section measuring tool to obtain cross section data at the calculated number of cross section measurement points, calculating the average measurement of the cross section measurement height, and calculating a calibration correction value that is a function of a difference between the average CD measurement of the object and the average measurement of the cross section measurement height of the object.

摘要翻译： 提供了一种方法和相应的系统，用于校准由不同测量工具测量的物体的数据，包括通过使用CD-SEM工具测量物体的临界尺寸（CD）和粗糙度，计算横截面数 校准所需的测量点，通过统计学处理物体的粗糙度，通过使用横截面测量工具测量物体的横截面，以在计算出的横截面测量点的数量上获得横截面数据，计算平均测量值 横截面测量高度，以及计算作为对象的平均CD测量与对象的横截面测量高度的平均测量之间的差的函数的校准校正值。

公开(公告)号：US20080319696A1

公开(公告)日：2008-12-25

申请号：US12137779

申请日：2008-06-12

申请人： Maki Tanaka ,  Wataru Nagatomo

发明人： Maki Tanaka ,  Wataru Nagatomo

IPC分类号： G01C25/00

CPC分类号： H01J37/263 ,  H01J37/222 ,  H01J2237/221 ,  H01J2237/24578 ,  H01J2237/24592 ,  H01J2237/2815 ,  H01J2237/2816 ,  H01J2237/2817 ,  H01J2237/2823 ,  H01J2237/2826

摘要： The present invention relates to a method and its system for calibrating measured data between different measuring tools. A method of calibrating measured data between different measuring tools includes the steps of: measuring the CD average dimension and roughness of an object to be measured using a CD-SEM tool; calculating the number of the cross section measurement points required for calibration by statistically processing the roughness; measuring the cross section of the object to be measured using the cross section measuring tool to satisfy the number of the cross section measurement points, thereby calculating the CD average dimension of the cross section measurement height specified in the obtained cross section measurement result; and calculating a calibration correction value being a difference between the CD average dimension of the object and the CD average dimension of the cross section measurement height of the object.

摘要翻译： 本发明涉及用于校准不同测量工具之间的测量数据的方法及其系统。 在不同测量工具之间校准测量数据的方法包括以下步骤：使用CD-SEM工具测量待测物体的CD平均尺寸和粗糙度; 通过统计处理粗糙度来计算校准所需的横截面测量点的数量; 使用截面测量工具测量被测量物体的横截面以满足横截面测量点的数量，从而计算得到的横截面测量结果中规定的横截面测量高度的CD平均尺寸; 并且计算校正校正值，该校正校正值是对象的CD平均尺寸与对象的横截面测量高度的CD平均尺寸之间的差。

公开(公告)号：US07449689B2

公开(公告)日：2008-11-11

申请号：US11260082

申请日：2005-10-28

申请人： Wataru Nagatomo ,  Ryoichi Matsuoka ,  Takumichi Sutani ,  Akiyuki Sugiyama ,  Yasuhiro Yoshitake ,  Hideaki Sasazawa

发明人： Wataru Nagatomo ,  Ryoichi Matsuoka ,  Takumichi Sutani ,  Akiyuki Sugiyama ,  Yasuhiro Yoshitake ,  Hideaki Sasazawa

IPC分类号： G03F1/00 ,  G21K7/00

CPC分类号： H01J37/28 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70625 ,  H01J37/222 ,  H01J2237/24578 ,  H01J2237/24592 ,  H01J2237/2817

摘要： The present invention relates to a dimension measuring SEM system and a circuit pattern evaluating system capable of achieving accurate, minute OPC evaluation, the importance of which increase with the progressive miniaturization of design pattern of a circuit pattern for a semiconductor device, and a circuit pattern evaluating method. Design data and measured data on an image of a resist pattern formed by photolithography are superposed for the minute evaluation of differences between a design pattern defined by the design data and the image of the resist pattern, and one- or two-dimensional geometrical features representing differences between the design pattern and the resist pattern are calculated. In some cases, the shape of the resist pattern differs greatly from the design pattern due to OPE effect (optical proximity effect). To superpose the design data and the measured data on the resist pattern stably and accurately, an exposure simulator calculates a simulated pattern on the basis of photomask data on a photomask for an exposure process and exposure conditions and superposes the simulated pattern and the image of the resist pattern.

摘要翻译： 本发明涉及一种尺寸测量SEM系统和电路图​​案评估系统，其能够实现精确的分钟OPC评估，其随着半导体器件的电路图案的设计图案的逐渐小型化以及电路图案的增加而增加的重要性 评估方法。 将通过光刻形成的抗蚀剂图案的图像上的设计数据和测量数据叠加以便对由设计数据定义的设计图案与抗蚀剂图案的图像之间的差异进行微小评估，以及表示一维或二维几何特征 计算设计图案和抗蚀剂图案之间的差异。 在某些情况下，由于OPE效应（光学邻近效应），抗蚀剂图案的形状与设计图案有很大的不同。 为了稳定准确地将设计数据和测量数据叠加在抗蚀剂图案上，曝光模拟器基于用于曝光处理和曝光条件的光掩模上的光掩模数据计算模拟图案，并将模拟图案和图像 抗蚀图案

公开(公告)号：US08971627B2

公开(公告)日：2015-03-03

申请号：US13696260

申请日：2011-03-17

申请人： Jun'ichi Taguchi ,  Mitsuji Ikeda ,  Yuichi Abe ,  Masahiro Kitazawa ,  Wataru Nagatomo

发明人： Jun'ichi Taguchi ,  Mitsuji Ikeda ,  Yuichi Abe ,  Masahiro Kitazawa ,  Wataru Nagatomo

IPC分类号： G06K9/00 ,  G06K9/62 ,  G01B11/00 ,  G01B15/00 ,  G06T7/00 ,  H01L21/66

CPC分类号： G06K9/6201 ,  G01B11/00 ,  G01B15/00 ,  G06K9/6202 ,  G06T7/001 ,  G06T7/74 ,  G06T2207/30148 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is a template matching processing device capable of evaluating a similarity degree which supports even a case of intensive morphological change between a design image and a photographic image. In the template matching processing device, matching processing between the design image and the photographic image is performed, a partial design image is obtained by clipping a portion having the highest correlation (step 101), and processing for deforming the photographic image in accordance with the clipped design image (steps 102 to 105) is performed, so that correlation between the deformed image obtained and the design image is taken to be set as the similarity degree.

摘要翻译： 本发明是一种模拟匹配处理装置，其能够评价即使在设计图像和摄影图像之间形成密集的情况的情况下也能够支持的相似度。 在模板匹配处理装置中，进行设计图像与摄影图像之间的匹配处理，通过剪切具有最高相关性的部分（步骤101）获得部分设计图像，以及根据 执行剪辑设计图像（步骤102至105），使得获得的变形图像与设计图像之间的相关性被设置为相似度。

公开(公告)号：US20140023265A1

公开(公告)日：2014-01-23

申请号：US13981963

申请日：2011-12-07

申请人： Masahiro Kitazawa ,  Mitsuji Ikeda ,  Yuichi Abe ,  Junichi Taguchi ,  Wataru Nagatomo

发明人： Masahiro Kitazawa ,  Mitsuji Ikeda ,  Yuichi Abe ,  Junichi Taguchi ,  Wataru Nagatomo

IPC分类号： G06T7/00

CPC分类号： G06T7/0004 ,  G06T7/001 ,  G06T2207/10061 ,  G06T2207/30148 ,  H01L22/12

摘要： It is an object of the present invention to provide a semiconductor inspection apparatus capable of well carrying out position alignment and correctly determining whether the position alignment has been carried out successfully or has ended in a failure without operator interventions even if an inspected image is an image having few characteristics as is the case with a repetitive pattern or the inspected image is an image having a complicated shape.The semiconductor inspection apparatus includes means for imaging a shape on a wafer or on an exposure mask; means for storing an image inspected by the imaging means; means for storing design data of the semiconductor circuit corresponding to a position on the wafer or on the exposure mask which are to be imaged by the imaging means; means for storing a design-data image obtained as a result of converting the design data into an image; means for generating a design-data ROI image by converting an interest drawing region found from a relative crude-density relation of a shape included in the design-data image into an image; and a position alignment section configured to carry out position alignment on the inspected image and the design-data image. The semiconductor inspection apparatus makes use of the design-data ROI image in order to identify a position at which the inspected image and the design-data image match each other or compute the degree of coincidence.

摘要翻译： 本发明的目的是提供一种半导体检查装置，即使被检查的图像是图像，也能够良好地执行位置对准并且正确地确定位置对准是否已经成功地执行或者在没有操作者干预的情况下已经结束 具有与重复图案的情况相同的特性，或被检查图像是具有复杂形状的图像。 半导体检查装置包括用于对晶片或曝光掩模上的形状进行成像的装置; 用于存储由成像装置检查的图像的装置; 用于存储对应于要由成像装置成像的晶片或曝光掩模上的位置的半导体电路的设计数据的装置; 用于存储作为将设计数据转换为图像而获得的设计数据图像的装置; 用于通过将从所述设计数据图像中包含的形状的相对粗密度关系中找到的兴趣绘制区域转换为图像来生成设计数据ROI图像的装置; 以及位置对准部，被配置为在被检查图像和设计数据图像上执行位置对准。 半导体检查装置利用设计数据ROI图像来识别被检查图像和设计数据图像彼此匹配的位置或计算符合度。

公开(公告)号：US20120207397A1

公开(公告)日：2012-08-16

申请号：US13502823

申请日：2010-10-06

申请人： Wataru Nagatomo ,  Yuichi Abe ,  Mitsuji Ikeda

发明人： Wataru Nagatomo ,  Yuichi Abe ,  Mitsuji Ikeda

IPC分类号： G06K9/68

CPC分类号： G06K9/6203 ,  G06K9/6253 ,  G06K9/6255 ,  G06K9/6857 ,  G06T7/74 ,  G06T2207/10061 ,  G06T2207/20016 ,  G06T2207/30148 ,  H01J2237/221 ,  H01J2237/226

摘要： Provided is a template matching method and a template matching apparatus, where the degree of matching between a template and the actual image upon template matching is maintained at a high level, without depending on a partial appearance of a lower layer. Proposed as one embodiment, is a method and an apparatus for template matching, where either an area is set in which comparison of the template and the image is not conducted, or a second area is set inside the template where comparison different from comparison conducted in a first comparison area is to be conducted, and the template matching is conducted on the basis either of comparison excluding the non-comparison area, or of comparison using the first and second areas.

摘要翻译： 提供了一种模板匹配方法和模板匹配装置，其中模板匹配之间的模板和实际图像之间的匹配程度保持在高水平，而不依赖于较低层的部分外观。 作为一个实施例，提出了一种用于模板匹配的方法和装置，其中设置了不进行模板和图像的比较的区域，或者在模板内部设置第二区域，其中比较不同于进行比较 将进行第一比较区域，并且基于除非比较区域之外的比较或使用第一和第二区域的比较进行模板匹配。