METHOD FOR PREVENTING TRENCHING IN FABRICATING SPLIT GATE FLASH DEVICES
    21.
    发明申请
    METHOD FOR PREVENTING TRENCHING IN FABRICATING SPLIT GATE FLASH DEVICES 有权
    用于防止在制造分离栅格闪存器件中进行TRENCHING的方法

    公开(公告)号:US20060275984A1

    公开(公告)日:2006-12-07

    申请号:US11141902

    申请日:2005-06-01

    IPC分类号: H01L21/336 H01L29/788

    摘要: A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying the masking layer. The light sensitive layer is patterned and etched to form a pattern of openings therein. The masking layer and the conductor layer are etched according to the pattern of openings in the light sensitive layer. The conductor layer is etched at the outer surface area between the conductor layer and the dielectric layer to form undercuts. The dielectric layer is etched to form a notch profile at the outer surface area between the conductor layer and the dielectric layer and portions of the substrate are etched to form a plurality of trenches. An isolation layer is filled over the plurality of trenches and the masking layer. The masking layer and portions of the conductor layer and isolation layer are etched away, wherein a portion of the isolation layer is preserved in the notch profile.

    摘要翻译: 提供了一种用于形成分离栅极闪光装置的方法。 在一个实施例中,提供了其上形成介电层的半导体衬底。 形成覆盖在电介质层上的导体层。 掩蔽层沉积在导体层上。 形成覆盖掩模层的光敏层。 对感光层进行图案化和蚀刻以在其中形成开口图案。 掩模层和导体层根据光敏层中的开口图案进行蚀刻。 在导体层和电介质层之间的外表面区域处蚀刻导体层以形成底切。 蚀刻电介质层以在导体层和电介质层之间的外表面区域形成切口轮廓,并且蚀刻衬底的部分以形成多个沟槽。 隔离层填充在多个沟槽和掩蔽层上。 掩模层和导体层和隔离层的部分被蚀刻掉,其中隔离层的一部分保留在凹口轮廓中。

    Novel process for erase improvement in a non-volatile memory device
    22.
    发明申请
    Novel process for erase improvement in a non-volatile memory device 有权
    用于擦除非易失性存储器件中的擦除的新方法

    公开(公告)号:US20060170029A1

    公开(公告)日:2006-08-03

    申请号:US11045850

    申请日:2005-01-28

    IPC分类号: H01L29/788

    摘要: A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate wherein the first mask layer has a plurality of openings in the cell region. Portions of the polycrystalline silicon layer exposed in the plurality of openings can be oxidized to form a plurality of poly-oxide regions, and the first mask layer can then be removed. The polycrystalline silicon layer not covered by the plurality of poly-oxide regions can be etched to form a plurality of floating gates, wherein etching the polycrystalline silicon layer is accompanied by a sputtering. A dielectric layer can then be formed, as well as a second mask layer in both the cell region and the peripheral region. The second mask layer in the cell region is partially etched back after a photoresist layer is formed over the second mask layer in the peripheral region. The dielectric layer is partially etched to form multiple thicknesses of the dielectric layer. The second mask layer is removed and a plurality of control gates are formed partially overlying the plurality of floating gates in the cell region.

    摘要翻译: 一种制造嵌入式非易失性存储器件的方法包括形成覆盖单元区域中的多晶硅层的第一掩模层和半导体衬底上的外围区域,其中第一掩模层在单元区域中具有多个开口。 在多个开口中暴露的多晶硅层的一部分可以被氧化以形成多个多晶氧化物区域,然后可以去除第一掩模层。 可以蚀刻不被多个多晶氧化物区域覆盖的多晶硅层以形成多个浮栅,其中蚀刻多晶硅层伴随着溅射。 然后可以形成电介质层,以及在电池区域和周边区域中形成第二掩模层。 在周边区域中的第二掩模层上形成光致抗蚀剂层之后,单元区域中的第二掩模层被部分地回蚀。 电介质层被部分蚀刻以形成介电层的多个厚度。 去除第二掩模层,并且多个控制栅极部分地覆盖在单元区域中的多个浮动栅极上。

    Phase change memory device with air gap
    23.
    发明授权
    Phase change memory device with air gap 有权
    具有气隙的相变存储器件

    公开(公告)号:US08288750B2

    公开(公告)日:2012-10-16

    申请号:US12770344

    申请日:2010-04-29

    IPC分类号: H01L29/04 H01L47/00

    摘要: A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided.

    摘要翻译: 提供一种半导体器件,其包括形成在衬底上的底部电极接触件和形成在底部电极接触件上的电介质层。 该装置还包括形成在电介质层中的加热元件,其中加热元件设置在将电加热元件与电介质层分开的两个气隙之间,以及形成在加热元件上的相变元件,其中相变元件包括 基本无定形背景和活性区域,该活性区域能够改变无定形和结晶之间的相。 还提供了一种形成这种装置的方法。

    SPACER STRUCTURE FOR TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SAME
    24.
    发明申请
    SPACER STRUCTURE FOR TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
    用于晶体管器件的间隔结构及其制造方法

    公开(公告)号:US20120056305A1

    公开(公告)日:2012-03-08

    申请号:US12874362

    申请日:2010-09-02

    IPC分类号: H01L29/73 H01L21/331

    摘要: The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.

    摘要翻译: 本公开提供了一种双极结型晶体管(BJT)器件和用于制造BJT器件的方法。 在一个实施例中,BJT器件包括:具有集电极区域和设置在半导体层上的材料层的半导体衬底。 材料层在其中具有暴露出集电极区域的一部分的沟槽。 基底结构,间隔物和发射体结构设置在材料层的沟槽内。 每个间隔物具有顶部宽度和底部宽度,顶部宽度基本上等于底部宽度。

    Phase Change Memory Device with Air Gap
    25.
    发明申请
    Phase Change Memory Device with Air Gap 有权
    具有空气间隙的相变存储器件

    公开(公告)号:US20110266511A1

    公开(公告)日:2011-11-03

    申请号:US12770344

    申请日:2010-04-29

    IPC分类号: H01L45/00 H01L21/20

    摘要: A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided.

    摘要翻译: 提供一种半导体器件,其包括形成在衬底上的底部电极接触件和形成在底部电极接触件上的电介质层。 该装置还包括形成在电介质层中的加热元件,其中加热元件设置在将电加热元件与电介质层分开的两个气隙之间,以及形成在加热元件上的相变元件,其中相变元件包括 基本无定形背景和活性区域,该活性区域能够改变无定形和结晶之间的相。 还提供了一种形成这种装置的方法。

    METHOD AND STRUCTURE FOR UNIFORM CONTACT AREA BETWEEN HEATER AND PHASE CHANGE MATERIAL IN PCRAM DEVICE
    26.
    发明申请
    METHOD AND STRUCTURE FOR UNIFORM CONTACT AREA BETWEEN HEATER AND PHASE CHANGE MATERIAL IN PCRAM DEVICE 有权
    PCRAT装置中加热器和相变材料之间的均匀接触面积的方法和结构

    公开(公告)号:US20090026432A1

    公开(公告)日:2009-01-29

    申请号:US11781728

    申请日:2007-07-23

    IPC分类号: H01L29/02 H01L21/20

    摘要: A PCM (phase change memory) cell in a PCRAM (phase change random access memory) semiconductor device includes a phase change material subjacently contacted by a heater film. The phase change material is formed over a surface that is a generally planar surface with at least a downwardly extending recess. The phase change material fills the recess and contacts the upper edge of the heater film that forms the bottom of the recess. After a planar surface is initially formed, a selective etching process is used to recede the top edge of the heater film below the planar surface using a selective and isotropic etching process.

    摘要翻译: PCRAM(相变随机存取存储器)半导体器件中的PCM(相变存储器)单元包括由加热膜隐藏接触的相变材料。 相变材料形成在具有至少一个向下延伸的凹部的大致平坦的表面的表面上。 相变材料填充凹部并接触形成凹部底部的加热器膜的上边缘。 在初始形成平坦表面之后,使用选择性蚀刻工艺来使用选择性和各向同性蚀刻工艺将加热器膜的顶部边缘退回到平坦表面下方。

    Process to improve programming of memory cells
    27.
    发明授权
    Process to improve programming of memory cells 有权
    改善存储单元编程的过程

    公开(公告)号:US07153755B2

    公开(公告)日:2006-12-26

    申请号:US11044813

    申请日:2005-01-26

    IPC分类号: H01L21/762

    摘要: A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.

    摘要翻译: 提供了一种用于制造半导体衬底的方法,该半导体衬底具有通过在衬底的表面上突出台阶高度的浅沟槽隔离(STI)结构彼此隔离的区域。 该方法包括以下步骤:形成覆盖半导体衬底的表面和STI结构表面的底部抗反射涂层(BARC)层; 蚀刻覆盖所述STI结构中的至少一个的所述BARC层的一部分,并且部分地蚀刻所述STI结构中的所述至少一个,以降低所述STI结构在所述衬底的表面上方突出的台阶高度; 以及去除相邻STI结构之间的BARC层的剩余部分。 该方法可用于制造包括具有改进的可靠性的存储器单元的半导体器件。

    Spacer structure for transistor device and method of manufacturing same
    29.
    发明授权
    Spacer structure for transistor device and method of manufacturing same 有权
    晶体管器件的间隔结构及其制造方法

    公开(公告)号:US08501572B2

    公开(公告)日:2013-08-06

    申请号:US12874362

    申请日:2010-09-02

    IPC分类号: H01L21/331

    摘要: The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.

    摘要翻译: 本公开提供了一种双极结型晶体管(BJT)器件和用于制造BJT器件的方法。 在一个实施例中,BJT器件包括:具有集电极区域和设置在半导体层上的材料层的半导体衬底。 材料层在其中具有暴露出集电极区域的一部分的沟槽。 基底结构,间隔物和发射体结构设置在材料层的沟槽内。 每个间隔物具有顶部宽度和底部宽度,顶部宽度基本上等于底部宽度。

    Method for forming MTJ cells
    30.
    发明授权
    Method for forming MTJ cells 有权
    形成MTJ细胞的方法

    公开(公告)号:US08278122B2

    公开(公告)日:2012-10-02

    申请号:US12696771

    申请日:2010-01-29

    IPC分类号: H01L21/00

    CPC分类号: H01L43/12 H01L27/222

    摘要: A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.

    摘要翻译: 形成集成电路结构的方法包括在衬底上形成底电极层; 在底部电极层上形成磁隧道结(MTJ)层; 图案化MTJ层以形成MTJ堆叠; 形成覆盖所述MTJ叠层的电介质层; 在所述电介质层中形成开口以暴露所述MTJ堆叠的一部分; 用顶部电极材料填充开口; 并对顶部电极材料进行平面化。 在执行平面化的步骤之后,对顶部电极材料和电介质层进行图案化,其中开口中的顶部电极材料的第一部分形成顶部电极,并且顶部电极材料的第二部分形成金属带 电介质层并连接到顶部电极。