公开(公告)号：US08278122B2

公开(公告)日：2012-10-02

申请号：US12696771

申请日：2010-01-29

申请人： Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  H01L27/222

摘要： A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.

摘要翻译： 形成集成电路结构的方法包括在衬底上形成底电极层; 在底部电极层上形成磁隧道结（MTJ）层; 图案化MTJ层以形成MTJ堆叠; 形成覆盖所述MTJ叠层的电介质层; 在所述电介质层中形成开口以暴露所述MTJ堆叠的一部分; 用顶部电极材料填充开口; 并对顶部电极材料进行平面化。 在执行平面化的步骤之后，对顶部电极材料和电介质层进行图案化，其中开口中的顶部电极材料的第一部分形成顶部电极，并且顶部电极材料的第二部分形成金属带 电介质层并连接到顶部电极。

公开(公告)号：US20110189796A1

公开(公告)日：2011-08-04

申请号：US12696771

申请日：2010-01-29

申请人： Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L43/12

CPC分类号： H01L43/12 ,  H01L27/222

摘要： A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.

摘要翻译： 形成集成电路结构的方法包括在衬底上形成底电极层; 在底部电极层上形成磁隧道结（MTJ）层; 图案化MTJ层以形成MTJ堆叠; 形成覆盖所述MTJ叠层的电介质层; 在所述电介质层中形成开口以暴露所述MTJ堆叠的一部分; 用顶部电极材料填充开口; 并对顶部电极材料进行平面化。 在执行平面化的步骤之后，对顶部电极材料和电介质层进行图案化，其中开口中的顶部电极材料的第一部分形成顶部电极，并且顶部电极材料的第二部分形成金属带 电介质层并连接到顶部电极。

公开(公告)号：US08921959B2

公开(公告)日：2014-12-30

申请号：US13190966

申请日：2011-07-26

申请人： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/82 ,  G11C11/00 ,  H01L21/00 ,  H01L43/12 ,  H01L43/08

CPC分类号： H01L43/12 ,  H01L43/08

摘要： According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.

摘要翻译： 根据实施例，磁阻随机存取存储器（MRAM）器件包括底部电极，堆叠，电介质材料，电介质层和导电材料。 底部电极在衬底上方，并且堆叠层在底部电极之上。 堆叠包括磁性隧道结（MTJ）和顶部电极。 介电材料沿着堆叠的侧壁，并且电介质材料具有高于MTJ的厚度并小于堆叠高度的高度。 电介质层在电池堆和电介质材料之上。 导电材料通过电介质层延伸到堆叠的顶部电极。

公开(公告)号：US08288750B2

公开(公告)日：2012-10-16

申请号：US12770344

申请日：2010-04-29

申请人： Ming-Huei Shen ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Ming-Huei Shen ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/04 ,  H01L47/00

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16

摘要： A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided.

摘要翻译： 提供一种半导体器件，其包括形成在衬底上的底部电极接触件和形成在底部电极接触件上的电介质层。 该装置还包括形成在电介质层中的加热元件，其中加热元件设置在将电加热元件与电介质层分开的两个气隙之间，以及形成在加热元件上的相变元件，其中相变元件包括 基本无定形背景和活性区域，该活性区域能够改变无定形和结晶之间的相。 还提供了一种形成这种装置的方法。

公开(公告)号：US20120056305A1

公开(公告)日：2012-03-08

申请号：US12874362

申请日：2010-09-02

申请人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/66287 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7378

摘要： The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.

摘要翻译： 本公开提供了一种双极结型晶体管（BJT）器件和用于制造BJT器件的方法。 在一个实施例中，BJT器件包括：具有集电极区域和设置在半导体层上的材料层的半导体衬底。 材料层在其中具有暴露出集电极区域的一部分的沟槽。 基底结构，间隔物和发射体结构设置在材料层的沟槽内。 每个间隔物具有顶部宽度和底部宽度，顶部宽度基本上等于底部宽度。

公开(公告)号：US20110266511A1

公开(公告)日：2011-11-03

申请号：US12770344

申请日：2010-04-29

申请人： Ming-Huei Shen ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Ming-Huei Shen ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L45/00 ,  H01L21/20

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16

摘要： A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided.

摘要翻译： 提供一种半导体器件，其包括形成在衬底上的底部电极接触件和形成在底部电极接触件上的电介质层。 该装置还包括形成在电介质层中的加热元件，其中加热元件设置在将电加热元件与电介质层分开的两个气隙之间，以及形成在加热元件上的相变元件，其中相变元件包括 基本无定形背景和活性区域，该活性区域能够改变无定形和结晶之间的相。 还提供了一种形成这种装置的方法。

公开(公告)号：US20090026432A1

公开(公告)日：2009-01-29

申请号：US11781728

申请日：2007-07-23

申请人： Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/02 ,  H01L21/20

CPC分类号： H01L45/16 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148

摘要： A PCM (phase change memory) cell in a PCRAM (phase change random access memory) semiconductor device includes a phase change material subjacently contacted by a heater film. The phase change material is formed over a surface that is a generally planar surface with at least a downwardly extending recess. The phase change material fills the recess and contacts the upper edge of the heater film that forms the bottom of the recess. After a planar surface is initially formed, a selective etching process is used to recede the top edge of the heater film below the planar surface using a selective and isotropic etching process.

摘要翻译： PCRAM（相变随机存取存储器）半导体器件中的PCM（相变存储器）单元包括由加热膜隐藏接触的相变材料。 相变材料形成在具有至少一个向下延伸的凹部的大致平坦的表面的表面上。 相变材料填充凹部并接触形成凹部底部的加热器膜的上边缘。 在初始形成平坦表面之后，使用选择性蚀刻工艺来使用选择性和各向同性蚀刻工艺将加热器膜的顶部边缘退回到平坦表面下方。

公开(公告)号：US07153755B2

公开(公告)日：2006-12-26

申请号：US11044813

申请日：2005-01-26

申请人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chien-Ming Ku ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Chia-Ta Hsieh

发明人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chien-Ming Ku ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Chia-Ta Hsieh

IPC分类号： H01L21/762

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/10894 ,  H01L27/11

摘要： A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.

摘要翻译： 提供了一种用于制造半导体衬底的方法，该半导体衬底具有通过在衬底的表面上突出台阶高度的浅沟槽隔离（STI）结构彼此隔离的区域。 该方法包括以下步骤：形成覆盖半导体衬底的表面和STI结构表面的底部抗反射涂层（BARC）层; 蚀刻覆盖所述STI结构中的至少一个的所述BARC层的一部分，并且部分地蚀刻所述STI结构中的所述至少一个，以降低所述STI结构在所述衬底的表面上方突出的台阶高度; 以及去除相邻STI结构之间的BARC层的剩余部分。 该方法可用于制造包括具有改进的可靠性的存储器单元的半导体器件。

公开(公告)号：US10553785B2

公开(公告)日：2020-02-04

申请号：US13452230

申请日：2012-04-20

申请人： Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16

摘要： This description relates to a method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of magnetic tunnel junction (MTJ) units. The method includes forming a bottom conductive layer, forming an anti-ferromagnetic layer and forming a tunnel layer over the bottom conductive layer and the anti-ferromagnetic layer. The method further includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer and forming a top conductive layer over the free magnetic layer. The method further includes performing at least one lithographic process to remove portions of the bottom conductive layer, the anti-ferromagnetic layer, the tunnel layer, the free magnetic layer and the top conductive layer that is uncovered by the photoresist layer until the bottom conductive layer is exposed and removing portions of at least one sidewall of the MTJ unit.

公开(公告)号：US08629531B2

公开(公告)日：2014-01-14

申请号：US13030645

申请日：2011-02-18

申请人： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L21/20 ,  H01L21/18

CPC分类号： H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/107 ,  H01L29/2003 ,  H01L29/66462 ,  H01L33/007 ,  H01L33/12

摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.

摘要翻译： 本公开提供了一种半导体结构。 所述半导体结构包括在硅衬底上的电介质材料层，所述电介质材料层被构图以限定由所述电介质材料层分隔的多个区域; 设置在所述硅衬底上的第一缓冲层; 设置在所述第一缓冲层上的异质缓冲层; 以及仅在多个区域内在异质缓冲层上生长的氮化镓层。