利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

77 条记录 (耗时 0.036 秒)

    METHODS OF AVOIDING WAFER BREAKAGE DURING MANUFACTURE OF BACKSIDE ILLUMINATED IMAGE SENSORS
    3.
    发明申请
    METHODS OF AVOIDING WAFER BREAKAGE DURING MANUFACTURE OF BACKSIDE ILLUMINATED IMAGE SENSORS 审中-公开
    在背光照明图像传感器制造过程中避免浪涌破裂的方法

    公开(公告)号：US20080044984A1

    公开(公告)日：2008-02-21

    申请号：US11465047

    申请日：2006-08-16

    申请人： Yuan-Chih Hsieh ,  Chung-Yi Yu ,  Gwo-Yuh Shiau ,  Shih-Chi Fu ,  Ming Chyi Liu ,  Chia-Shiung Tsai

    发明人： Yuan-Chih Hsieh ,  Chung-Yi Yu ,  Gwo-Yuh Shiau ,  Shih-Chi Fu ,  Ming Chyi Liu ,  Chia-Shiung Tsai

    IPC分类号： H01L21/30 ,  H01L21/46

    CPC分类号： H01L21/304 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A process for forming backside illuminated devices is disclosed. Specifically, the process reduces processing damage to wafers caused by poor bond quality at the wafer edge ring. In one embodiment, a wafer edge trimming step is implemented prior to bonding the wafer to the substrate. A pre-grind blade is used to create a straight edge around the wafer perimeter, eliminating any sharp edges. In another embodiment, edge trimming is performed after the wafer has been bonded to the substrate, and a pre-grind blade is used to remove portion of the wafer edge ring subject to poor bonding quality before grinding. The final thickness of the ground wafer is about 50 microns in either case.

    摘要翻译： 公开了一种用于形成背面照明装置的工艺。 具体地说，该方法减少了由于晶片边缘环上的接合质量差而导致的对晶片的加工损坏。 在一个实施例中，在将晶片接合到基板之前实现晶片边缘修剪步骤。 预磨刀片用于在晶片周边周围创建直边，消除任何尖锐边缘。 在另一个实施例中，在晶片已经结合到基板之后进行边缘修整，并且在研磨之前使用预研磨刀片来去除在接合质量差的条件下的部分晶片边缘环。 在任一情况下，接地晶片的最终厚度为约50微米。

    Image sensor device suitable for use with logic-embedded CIS chips and methods for making the same
    6.
    发明授权
    Image sensor device suitable for use with logic-embedded CIS chips and methods for making the same 有权
    适用于逻辑嵌入式CIS芯片的图像传感器装置及其制造方法

    公开(公告)号：US07544982B2

    公开(公告)日：2009-06-09

    申请号：US11542064

    申请日：2006-10-03

    申请人： Chung-Yi Yu ,  Chia-Shiung Tsai ,  Shih-Chi Fu

    发明人： Chung-Yi Yu ,  Chia-Shiung Tsai ,  Shih-Chi Fu

    IPC分类号： H01L31/062

    CPC分类号： H01L27/14627 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687

    摘要： An image sensor device is provided. A substrate has a photosensor region formed therein and/or thereon. An interconnection structure is formed over the substrate, and includes metal lines formed in inter-metal dielectric (IMD) layers. At least one IMD-level micro-lens is/are formed in at least one of the IMD layers over the photosensor region. Preferably, barrier layers are located between the IMD layers. Preferably, each of the barrier layers at each level has a net thickness limited to 100 angstroms or less at locations over the photosensor region, except at locations where the IMD-level micro-lenses are located. The IMD-level micro-lenses and the etch stop layers preferably have a refractive index greater than that of the IMD layers. A cap layer is preferably formed on the metal lines, especially when the metal lines include copper. An upper-level micro-lens may be located on a level that is above the interconnection structure.

    摘要翻译： 提供图像传感器装置。 衬底在其中和/或其上形成有光电传感器区域。 在衬底上形成互连结构，并且包括在金属间电介质（IMD）层中形成的金属线。 在光电传感器区域中的至少一个IMD层中形成至少一个IMD级微透镜。 优选地，阻挡层位于IMD层之间。 优选地，除了在IMD级微透镜所在的位置之外，每个级别的每个阻挡层的净厚度在光电传感器区域之外的位置处具有限制在100埃或更小的净厚度。 IMD级微透镜和蚀刻停止层优选具有大于IMD层的折射率的折射率。 优选在金属线上形成覆盖层，特别是当金属线包括铜时。 上级微透镜可以位于互连结构之上的层上。

    Image sensor device suitable for use with logic-embedded CIS chips and methods for making the same
    7.
    发明申请
    Image sensor device suitable for use with logic-embedded CIS chips and methods for making the same 有权
    适用于逻辑嵌入式CIS芯片的图像传感器装置及其制造方法

    公开(公告)号：US20080087921A1

    公开(公告)日：2008-04-17

    申请号：US11542064

    申请日：2006-10-03

    申请人： Chung-Yi Yu ,  Chia-Shiung Tsai ,  Shih-Chi Fu

    发明人： Chung-Yi Yu ,  Chia-Shiung Tsai ,  Shih-Chi Fu

    IPC分类号： H01L29/76 ,  H01L29/745

    CPC分类号： H01L27/14627 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687

    摘要： An image sensor device is provided. A substrate has a photosensor region formed therein and/or thereon. An interconnection structure is formed over the substrate, and includes metal lines formed in inter-metal dielectric (IMD) layers. At least one IMD-level micro-lens is/are formed in at least one of the IMD layers over the photosensor region. Preferably, barrier layers are located between the IMD layers. Preferably, each of the barrier layers at each level has a net thickness limited to 100 angstroms or less at locations over the photosensor region, except at locations where the IMD-level micro-lenses are located. The IMD-level micro-lenses and the etch stop layers preferably have a refractive index greater than that of the IMD layers. A cap layer is preferably formed on the metal lines, especially when the metal lines include copper. An upper-level micro-lens may be located on a level that is above the interconnection structure.

    摘要翻译： 提供图像传感器装置。 衬底在其中和/或其上形成有光电传感器区域。 在衬底上形成互连结构，并且包括在金属间电介质（IMD）层中形成的金属线。 在光电传感器区域中的至少一个IMD层中形成至少一个IMD级微透镜。 优选地，阻挡层位于IMD层之间。 优选地，除了在IMD级微透镜所在的位置之外，每个级别的每个阻挡层的净厚度在光电传感器区域之外的位置处具有限制在100埃或更小的净厚度。 IMD级微透镜和蚀刻停止层优选具有大于IMD层的折射率的折射率。 优选在金属线上形成覆盖层，特别是当金属线包括铜时。 上级微透镜可以位于互连结构之上的层上。

    Split-gate memory cells and fabrication methods thereof
    8.
    发明申请
    Split-gate memory cells and fabrication methods thereof 有权
    分离栅存储单元及其制造方法

    公开(公告)号：US20080121975A1

    公开(公告)日：2008-05-29

    申请号：US11592290

    申请日：2006-11-03

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

    Split-gate memory cells and fabrication methods thereof
    9.
    发明申请
    Split-gate memory cells and fabrication methods thereof 失效
    分离栅存储单元及其制造方法

    公开(公告)号：US20080105917A1

    公开(公告)日：2008-05-08

    申请号：US11785382

    申请日：2007-04-17

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788 ,  H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。 活动区域的顶层低于隔离区域的顶层。 一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。 一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。