公开(公告)号：US08389410B2

公开(公告)日：2013-03-05

申请号：US13087356

申请日：2011-04-14

申请人： Kun-Lin Wu ,  Meng-Jin Tsai

发明人： Kun-Lin Wu ,  Meng-Jin Tsai

IPC分类号： H01L21/302

CPC分类号： H01L21/76829 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76819 ,  H01L21/7684

摘要： A chemical-mechanical polishing process includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

摘要翻译： 化学机械抛光工艺包括以下步骤：提供其上具有第一导电线的半导体衬底，然后在衬底和第一导电线上形成至少一个电介质层。 接下来，使用化学 - 机械抛光方法来抛光电介质层的表面。 此后，在抛光的介电层上形成覆盖层。 形成盖层的方法包括使用硅烷（SiH4）或四乙基原硅酸盐（TEOS）作为主要反应剂的化学气相沉积法沉积氧化硅。 或者，可以通过使用化学气相沉积法以硅烷或二氯硅酸氢钠（SiH 2 Cl 2）作为主要反应剂沉积氮化硅来形成覆盖层。 最后，通过介电层和盖层形成通孔，以及通过通路孔与第一导电线电连接的第二导线。

公开(公告)号：US07947603B2

公开(公告)日：2011-05-24

申请号：US11965757

申请日：2007-12-28

申请人： Kun-Lin Wu ,  Meng-Jin Tsai

发明人： Kun-Lin Wu ,  Meng-Jin Tsai

IPC分类号： H01L21/302

CPC分类号： H01L21/76829 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76819 ,  H01L21/7684

摘要： A chemical-mechanical polishing process for forming a conductive interconnect includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH.sub.4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH.sub.2Cl.sub.2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

摘要翻译： 用于形成导电互连的化学机械抛光工艺包括以下步骤：提供其上具有第一导电线的半导体衬底，然后在衬底和第一导电线上形成至少一个电介质层。 接下来，使用化学 - 机械抛光方法来抛光电介质层的表面。 此后，在抛光的介电层上形成覆盖层。 形成盖层的方法包括使用硅烷（SiH 4）或四乙基原硅酸盐（TEOS）作为主要反应剂的化学气相沉积法沉积氧化硅。 或者，可以通过使用化学气相沉积法以硅烷或二氯硅氢化钠（SiH 2 Cl 2）作为主要反应剂沉积氮化硅来形成覆盖层。 最后，通过介电层和盖层形成通孔，以及通过通路孔与第一导电线电连接的第二导线。

公开(公告)号：US06281694B1

公开(公告)日：2001-08-28

申请号：US09449662

申请日：1999-11-30

申请人： Meng-Jin Tsai

发明人： Meng-Jin Tsai

IPC分类号： G01R3102

CPC分类号： G01R35/00 ,  G01R1/07307

摘要： A monitor method for testing probe pins is described in this invention. In accordance with the method of the present invention, a particular probe pin with short, deformity or unstable contact is identified.

摘要翻译： 在本发明中描述了用于测试探针的监视器方法。 根据本发明的方法，识别出具有短，变形或不稳定接触的特定探针。

公开(公告)号：US06268266B1

公开(公告)日：2001-07-31

申请号：US09425600

申请日：1999-10-22

申请人： Ching-Chun Hwang ,  Fei-Hung Chen ,  Meng-Jin Tsai ,  Wei-Chung Chen

发明人： Ching-Chun Hwang ,  Fei-Hung Chen ,  Meng-Jin Tsai ,  Wei-Chung Chen

IPC分类号： H01L2176

CPC分类号： H01L21/76202 ,  H01L21/76213 ,  H01L21/823462 ,  H01L21/823481

摘要： A method for forming enhanced field oxide (FOX) region of low voltage devices in a high voltage process is disclosed. The method includes providing a semiconductor structure comprising a substrate, two field oxide regions on the substrate, a well between the two field oxide regions in the substrate and a silicon nitride layer between the two field oxide regions above the well. As a key step, nitrogen is implanted into the semiconductor structure, and the silicon nitride layer is then removed. Then, a gate oxide layer on the well and silicon oxynitride layer on the field oxide regions are all formed in-situ.

摘要翻译： 公开了一种用于在高电压工艺中形成低电压器件的增强型场氧化物（FOX）区域的方法。 该方法包括提供包括衬底的半导体结构，衬底上的两个场氧化物区域，衬底中的两个场氧化物区域之间的阱以及阱上方的两个场氧化物区域之间的氮化硅层。 作为关键步骤，将氮注入到半导体结构中，然后除去氮化硅层。 然后，在场氧化物区域上的阱和氧氮化硅层上的栅极氧化物层全部原位形成。

公开(公告)号：US6140156A

公开(公告)日：2000-10-31

申请号：US352478

申请日：1999-07-13

申请人： Meng-Jin Tsai

发明人： Meng-Jin Tsai

IPC分类号： H01L21/339

CPC分类号： H01L27/14683 ,  H01L27/1463

摘要： A method for fabricating a photodiode is described in which a pad oxide layer and a silicon nitride layer are sequentially formed on a provided substrate. The silicon nitride layer, and the pad oxide layer and the substrate are sequentially patterned to form an opening in the substrate. A spacer is formed on the sidewall of the opening. With the spacer and the silicon nitride layer serving as a mask, the substrate is etched forming a trench in the substrate. An oxide plug is then formed filling the trench and the opening using the conventional shallow trench fabrication method. A P-well region and an N-well region are formed respectively on two sides of the trench. An N+ type region and a P+ type region are formed respectively on two sides of the opening; wherein the N+ type region is located above the P-well region and the P+ type region is located above the N-well region

摘要翻译： 描述了一种用于制造光电二极管的方法，其中衬垫氧化物层和氮化硅层依次形成在所提供的衬底上。 氮化硅层和衬垫氧化物层和衬底被顺序地图案化以在衬底中形成开口。 间隔件形成在开口的侧壁上。 通过间隔物和氮化硅层作为掩模，蚀刻衬底在衬底中形成沟槽。 然后使用常规浅沟槽制造方法形成填充沟槽和开口的氧化物塞。 分别在沟槽的两侧形成P阱区域和N阱区域。 分别在开口的两侧形成N +型区域和P +型区域; 其中所述N +型区域位于所述P阱区域上方，并且所述P +型区域位于所述N阱区域上方

公开(公告)号：US6114220A

公开(公告)日：2000-09-05

申请号：US195226

申请日：1998-11-18

申请人： Meng-Jin Tsai

发明人： Meng-Jin Tsai

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76229 ,  Y10S148/05

摘要： A method of fabricating a shallow trench isolation includes formation of a trench in a substrate. An oxide layer is formed on the substrate to fill the trench. A barrier layer and a coating layer are formed in sequence over the substrate. A first etching step is performed to remove a portion of the coating layer and the oxide layer to at least expose the oxide layer on the mask layer. A second etching step is performed to remove the other portion of the coating layer and the oxide layer until exposing the mask layer. Thus, micro-scratches and defects do not happen and thus the invention prevents the occurrence of bridging effect and short circuits.

摘要翻译： 制造浅沟槽隔离的方法包括在衬底中形成沟槽。 在衬底上形成氧化层以填充沟槽。 在衬底上依次形成阻挡层和涂层。 执行第一蚀刻步骤以去除涂层和氧化物层的一部分，以至少暴露掩模层上的氧化物层。 执行第二蚀刻步骤以除去涂层和氧化物层的另一部分，直到暴露掩模层。 因此，不会发生微小划伤和缺陷，因此本发明防止桥接效应和短路的发生。

公开(公告)号：US06037201A

公开(公告)日：2000-03-14

申请号：US040215

申请日：1998-03-17

申请人： Meng-Jin Tsai ,  Cheng-Han Huang

发明人： Meng-Jin Tsai ,  Cheng-Han Huang

IPC分类号： H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28167 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/28194 ,  Y10S148/163

摘要： A method for manufacturing mixed-mode devices that can eliminate watermarks resulting from the formation of residues at the dead corner space of an inverted trapezium-shaped structure at the upper end of a shallow trench during dual gate-oxide processing operation. This method uses the same chemical processing conditions for etching the oxide layer and the removal of photoresist layer, so that no watermarks remain after the etching and cleaning processes. MOS transistors are formed over the thin gate oxide layer region and the thick gate oxide region are of, two types, each having a different gate oxide layer thickness so that each has a different operating voltage.

摘要翻译： 一种用于制造混合模式装置的方法，其可以消除在双栅极氧化物处理操作期间在浅沟槽的上端处的倒梯形结构的死角空间处形成残留物所产生的水印。 该方法使用相同的化学处理条件来蚀刻氧化物层和去除光致抗蚀剂层，使得在蚀刻和清洁工艺之后不会保留水印。 在薄栅极氧化物层区域上形成MOS晶体管，厚栅极氧化物区域分别具有不同的栅极氧化层厚度，每个具有不同的工作电压。

公开(公告)号：US5981379A

公开(公告)日：1999-11-09

申请号：US139872

申请日：1998-08-25

申请人： Meng-Jin Tsai

发明人： Meng-Jin Tsai

IPC分类号： H01L21/768 ,  H01L21/4763 ,  H01L21/302 ,  H01L23/48

CPC分类号： H01L21/76816 ,  H01L21/76807 ,  H01L21/76829

摘要： A method of forming a via. A substrate having a first conductive layer thereon is provided. An inter-metal dielectric layer is formed over the substrate layer by high density plasma chemical vapor deposition. An etch stop layer is formed on the inter-metal dielectric layer. An oxide layer is formed on the etch stop layer. The oxide layer is defined, so that a shallow opening aligned with the first conductive layer is formed to exposed the inter-metal dielectric layer. The inter-metal dielectric layer is etched away within the shallow opening until the first conductive layer is exposed. The opening is filled with a second conductive layer. The oxide layer is defined by photolithography and etching with a first selectivity, with which the oxide layer has a comparable etching rate to the etch stop layer. The inter-metal dielectric layer is etched with a second selectivity, with which the inter-metal dielectric layer has an etching rate higher than the etch stop layer.

摘要翻译： 形成通孔的方法。 提供其上具有第一导电层的基板。 通过高密度等离子体化学气相沉积在衬底层上形成金属间介电层。 在金属间介电层上形成蚀刻停止层。 在蚀刻停止层上形成氧化物层。 限定氧化物层，使得形成与第一导电层对准的浅开口以暴露金属间介电层。 在浅开口内蚀刻金属间介电层，直到暴露第一​​导电层。 开口填充有第二导电层。 通过光刻和第一选择性蚀刻来限定氧化物层，氧化物层具有与蚀刻停止层相当的蚀刻速率。 以第二选择性蚀刻金属间介电层，金属间电介质层具有比蚀刻停止层更高的蚀刻速率。

公开(公告)号：US5965464A

公开(公告)日：1999-10-12

申请号：US989757

申请日：1997-12-12

申请人： Meng-Jin Tsai ,  Cheng-Han Huang ,  Te-Chuan Liao ,  Chen-Wei Lee

发明人： Meng-Jin Tsai ,  Cheng-Han Huang ,  Te-Chuan Liao ,  Chen-Wei Lee

IPC分类号： H01L21/8234 ,  H01L21/302

CPC分类号： H01L21/823468

摘要： A method for forming a double spacer structure comprising the steps of first providing a semiconductor substrate that has a first gate and a second gate already formed thereon, wherein the gate length of the second gate is greater than the gate length of the first gate. Then, a first insulating layer is formed over the substrate and the gates. Next, a photoresist layer is formed over the first insulating layer above the second gate while exposing the first insulating layer above the first gate. Subsequently, a first etching operation is performed to establish a first spacer structure along the sidewalls of the first gate, and then the photoresist layer is removed leaving the first insulating layer over the second gate. Thereafter, a second insulating layer is formed over the substrate, the first gate and the first insulating layer, and then a second etching operation is performed to establish a second spacer structure along the sidewalls of the second gate. Therefore, a second spacer that has a width greater than the first spacer does is finally obtained.

摘要翻译： 一种形成双间隔结构的方法，包括以下步骤：首先提供半导体衬底，该半导体衬底具有已经形成在其上的第一栅极和第二栅极，其中第二栅极的栅极长度大于第一栅极的栅极长度。 然后，在衬底和栅极上形成第一绝缘层。 接下来，在第一栅极上方的第一绝缘层上方形成光致抗蚀剂层，同时使第一绝缘层暴露在第一栅极之上。 随后，执行第一蚀刻操作以沿着第一栅极的侧壁建立第一间隔结构，然后去除光致抗蚀剂层，离开第二绝缘层在第二栅极上。 此后，在衬底，第一栅极和第一绝缘层上形成第二绝缘层，然后进行第二蚀刻操作，以沿着第二栅极的侧壁建立第二间隔结构。 因此，最终获得具有大于第一间隔物的宽度的第二间隔物。

公开(公告)号：US5937291A

公开(公告)日：1999-08-10

申请号：US870202

申请日：1997-06-06

申请人： Meng-Jin Tsai ,  Kun-Cho Chen

发明人： Meng-Jin Tsai ,  Kun-Cho Chen

IPC分类号： H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/8234

CPC分类号： H01L27/11 ,  H01L21/76895 ,  H01L27/1108 ,  Y10S438/953

摘要： A manufacturing method applicable for forming a via connection to the thin film transistor in a SRAM unit which resolves the problems arising from a conventional method for forming a via for linking up the drain of a load transistor with the gate of a driver transistor in a SRAM unit by changing the processing sequence and also by forming a plug instead of a via.

摘要翻译： 一种适用于在SRAM单元中形成与薄膜晶体管的通孔连接的制造方法，该SRAM单元解决了用于形成用于将负载晶体管的漏极与SRAM中的驱动晶体管的栅极连接的通孔的常规方法所引起的问题 通过改变处理顺序并且还通过形成插头而不是通孔来实现。