公开(公告)号：US20070202637A1

公开(公告)日：2007-08-30

申请号：US11742147

申请日：2007-04-30

申请人： Jack Mandelman ,  Louis Hsu ,  Rajiv Joshi

发明人： Jack Mandelman ,  Louis Hsu ,  Rajiv Joshi

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1203 ,  H01L29/94

摘要： A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

摘要翻译： 提供一种具有体电容板的半导体结构，其形成有确保体电容板与源极线（SL）扩散和位线扩散两者自对准的工艺。 因此，SL和位线扩散和体电容板之间的重叠量被精确地控制。 更具体地说，本发明通过使用确保存在1）板和源极/漏极扩散之间的最小重叠的过程形成具有侧壁电容器板的1T无电容的SOI体电荷存储单元的结构，以及2）最小重叠 在本发明中获得的精确控制并且不受对准公差的影响。 与现有技术相比，本发明的电池产生更大的信号余量，改善的性能，更小的芯片尺寸和降低的动态功耗。

公开(公告)号：US20060189110A1

公开(公告)日：2006-08-24

申请号：US11064730

申请日：2005-02-24

申请人： Jack Mandelman ,  Louis Hsu ,  Rajiv Joshi

发明人： Jack Mandelman ,  Louis Hsu ,  Rajiv Joshi

IPC分类号： H01L21/3205

CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1203 ,  H01L29/94

摘要： A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

摘要翻译： 提供一种具有体电容板的半导体结构，其形成有确保体电容板与源极线（SL）扩散和位线扩散两者自对准的工艺。 因此，SL和位线扩散和体电容板之间的重叠量被精确地控制。 更具体地说，本发明通过使用确保存在1）板和源极/漏极扩散之间的最小重叠的过程形成具有侧壁电容器板的1T无电容的SOI体电荷存储单元的结构，以及2）最小重叠 在本发明中获得的精确控制并且不受对准公差的影响。 与现有技术相比，本发明的电池产生更大的信号余量，改善的性能，更小的芯片尺寸和降低的动态功耗。

公开(公告)号：US20050042835A1

公开(公告)日：2005-02-24

申请号：US10643307

申请日：2003-08-19

申请人： Louis Hsu ,  Rajiv Joshi ,  Chun-Yung Sung

发明人： Louis Hsu ,  Rajiv Joshi ,  Chun-Yung Sung

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L21/20 ,  H01L21/8242

CPC分类号： H01G4/228 ,  H01G4/33 ,  H01L21/768 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insultaing layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.

摘要翻译： 一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层 沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。 一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少在第一绝缘层中形成第一开口和至少第二开口，在第二开口上沉积掩模 在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。 描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

公开(公告)号：US20090111235A1

公开(公告)日：2009-04-30

申请号：US12348707

申请日：2009-01-05

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/02

CPC分类号： H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

公开(公告)号：US20080023789A1

公开(公告)日：2008-01-31

申请号：US11834841

申请日：2007-08-07

申请人： Louis Hsu ,  Conal Murray ,  Chaudrasekhar Narayan ,  Chih-Chao Yang

发明人： Louis Hsu ,  Conal Murray ,  Chaudrasekhar Narayan ,  Chih-Chao Yang

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  G11C16/02 ,  G11C17/16 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a reprogrammable electrically blowable fuse. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.

摘要翻译： 本发明提供一种可再编程的可电熔熔断器。 电可熔熔丝使用电迁移效应进行编程，并使用反向电迁移效应重新编程。 可电熔熔丝的状态（即“打开”或“关闭”）由将电可电熔丝的电阻与参考电阻进行比较的感测系统确定。

公开(公告)号：US20070235833A1

公开(公告)日：2007-10-11

申请号：US11393142

申请日：2006-03-30

申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

IPC分类号： H01L29/00

CPC分类号： H01L27/10841 ,  H01L27/10864

摘要： Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.

摘要翻译： 具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法。 半导体结构包括限定在与沟槽的侧壁相邻的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。 半导体材料的中间区域分离第一和第二掺杂区域。 第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。 第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。 用于形成掺杂区域的方法包括沉积掺杂有掺杂剂或不同层的材料的层，每个掺杂剂或不同的层在沟槽中掺杂有一种掺杂剂，然后将掺杂剂从层或层扩散到与沟槽接壤的半导体材料 侧壁。

公开(公告)号：US20070210890A1

公开(公告)日：2007-09-13

申请号：US11372387

申请日：2006-03-09

申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

IPC分类号： H01H85/04

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  Y10T29/49107 ,  H01L2924/00

摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.

摘要翻译： 本发明提供一种用于集成电路的电子熔断器及其制造方法。 电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。 保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。 制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。 电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

公开(公告)号：US20070035342A1

公开(公告)日：2007-02-15

申请号：US11203860

申请日：2005-08-15

申请人： Minhan Chen ,  Westerfield Ficken ,  Louis Hsu ,  Steven Zier

发明人： Minhan Chen ,  Westerfield Ficken ,  Louis Hsu ,  Steven Zier

IPC分类号： H03F3/45

CPC分类号： H03F3/45197 ,  H03F2203/45424 ,  H03F2203/45431 ,  H03F2203/45488 ,  H03F2203/45646

摘要： Offset voltages in differential amplifiers are minimized by controlling compensation currents through the load impedances of the amplifiers. The currents are varied while sensing the polarity of the offset voltage. When the polarity changes, the current values are latched to keep the offset voltage at a minimum.

公开(公告)号：US20060284251A1

公开(公告)日：2006-12-21

申请号：US11155030

申请日：2005-06-16

申请人： Louis Hsu ,  Jack Mandelman

发明人： Louis Hsu ,  Jack Mandelman

IPC分类号： H01L27/12

CPC分类号： H01L29/045 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207

摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.

公开(公告)号：US20060284250A1

公开(公告)日：2006-12-21

申请号：US11154906

申请日：2005-06-16

申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti

发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/045

摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.