公开(公告)号：US20080023789A1

公开(公告)日：2008-01-31

申请号：US11834841

申请日：2007-08-07

申请人： Louis Hsu ,  Conal Murray ,  Chaudrasekhar Narayan ,  Chih-Chao Yang

发明人： Louis Hsu ,  Conal Murray ,  Chaudrasekhar Narayan ,  Chih-Chao Yang

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  G11C16/02 ,  G11C17/16 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a reprogrammable electrically blowable fuse. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.

摘要翻译： 本发明提供一种可再编程的可电熔熔断器。 电可熔熔丝使用电迁移效应进行编程，并使用反向电迁移效应重新编程。 可电熔熔丝的状态（即“打开”或“关闭”）由将电可电熔丝的电阻与参考电阻进行比较的感测系统确定。

公开(公告)号：US20070281469A1

公开(公告)日：2007-12-06

申请号：US11839258

申请日：2007-08-15

申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

公开(公告)号：US20060249808A1

公开(公告)日：2006-11-09

申请号：US10908245

申请日：2005-05-04

申请人： Louis Hsu ,  Conal Murray ,  Chandrasekhar Narayan ,  Chih-Chao Yang

发明人： Louis Hsu ,  Conal Murray ,  Chandrasekhar Narayan ,  Chih-Chao Yang

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  G11C16/02 ,  G11C17/16 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a reprogrammable electrically blowable fuse. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.

摘要翻译： 本发明提供一种可再编程的可电熔熔断器。 电可熔熔丝使用电迁移效应进行编程，并使用反向电迁移效应重新编程。 可电熔熔丝的状态（即“打开”或“关闭”）由将电可电熔丝的电阻与参考电阻进行比较的感测系统确定。

公开(公告)号：US20060081986A1

公开(公告)日：2006-04-20

申请号：US10964882

申请日：2004-10-14

申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L23/52

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

公开(公告)号：US20060231945A1

公开(公告)日：2006-10-19

申请号：US10907873

申请日：2005-04-19

申请人： Anil Chinthakindi ,  Lawrence Clevenger ,  Tom Lee ,  Gerald Matusiewicz ,  Conal Murray ,  Chih-Chao Yang

发明人： Anil Chinthakindi ,  Lawrence Clevenger ,  Tom Lee ,  Gerald Matusiewicz ,  Conal Murray ,  Chih-Chao Yang

IPC分类号： H01L23/34

CPC分类号： H01L23/5228 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method are disclosed for heat dissipation relative to a heat generating element in a semiconductor device. The structure includes a plurality of heat transmitting lines partially vertically coincidental with the heat generating element, and at least one interconnecting path from each heat transmitting line to a substrate of the semiconductor device. In one embodiment, the heat generating element includes a resistor in a non-first metal level. The invention is compatible with conventional BEOL interconnect schemes, minimizes the amount of heat transfer from the resistor to the surrounding interconnect wiring, thus eliminating the loss of current carrying capability in the wiring.

摘要翻译： 公开了相对于半导体器件中的发热元件的散热的结构和方法。 该结构包括多个与发热元件垂直一致的传热线，以及从每个传热线到半导体器件的基板的至少一个互连路径。 在一个实施例中，发热元件包括非第一金属水平的电阻器。 本发明与传统的BEOL互连方案兼容，使得从电阻器到周围互连布线的传热量最小化，从而消除了布线中的载流能力的损失。

公开(公告)号：US20070010093A1

公开(公告)日：2007-01-11

申请号：US11160699

申请日：2005-07-06

申请人： Yun-Yu Wang ,  Christian Lavoie ,  Kevin Mello ,  Conal Murray ,  Matthew Oonk

发明人： Yun-Yu Wang ,  Christian Lavoie ,  Kevin Mello ,  Conal Murray ,  Matthew Oonk

IPC分类号： G01R31/26 ,  H01L21/44 ,  H01L21/66

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76834

摘要： Silicide is protected during MC RIE etch by first forming an oxide film over the silicide and, after performing MC RIE etch, etching the oxide film. The oxide film is formed from a film of alloyed metal-silicon (M-Si) on the layer of silicide, then wet etching the metal-silicon. An ozone plasma treatment process can be an option to densify the oxide film. The oxide film may be etched by oxide RIE or wet etch, using 500:1 DHF.

摘要翻译： 在MC RIE蚀刻期间，硅化物被保护，首先在硅化物上形成氧化膜，并且在执行MC RIE蚀刻之后蚀刻氧化物膜。 氧化膜由硅化物层上的合金化金属硅（M-Si）的膜形成，然后湿式蚀刻金属硅。 臭氧等离子体处理方法可以是使氧化膜致密化的选择。 可以使用500:1的DHF，通过氧化物RIE或湿法蚀刻来蚀刻氧化膜。

公开(公告)号：US20060169894A1

公开(公告)日：2006-08-03

申请号：US11037613

申请日：2005-01-18

申请人： Lynne Gignac ,  Conal Murray ,  Oliver Wells

发明人： Lynne Gignac ,  Conal Murray ,  Oliver Wells

IPC分类号： G21K7/00 ,  G01N23/00

CPC分类号： G01N23/225 ,  H01J37/244 ,  H01J2237/2446 ,  H01J2237/24495 ,  H01J2237/28

摘要： An imaging device having many detector elements is used to construct multiple images of the surface of a specimen in a scanning electron microscope (SEM) using signals from different elements of the imaging device as the specimen is scanned a single time in the SEM.

摘要翻译： 使用具有许多检测器元件的成像装置使用来自成像装置的不同元件的信号在扫描电子显微镜（SEM）中构建样品表面的多个图像，因为在SEM中单次扫描样品。

公开(公告)号：US20070174796A1

公开(公告)日：2007-07-26

申请号：US11336524

申请日：2006-01-20

申请人： Matthew Angyal ,  Giovanni Fiorenza ,  Habib Hichri ,  Andrew Lu ,  Dale McHerron ,  Conal Murray

发明人： Matthew Angyal ,  Giovanni Fiorenza ,  Habib Hichri ,  Andrew Lu ,  Dale McHerron ,  Conal Murray

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.

摘要翻译： 用于分析电路设计的系统，方法和计算机程序产品提供将电路设计离散成一系列像素。 确定每个像素的至少一个构成材料的一部分。 还为每个像素确定偏转。 该偏转基于像素的平面化，并且在利用包括至少一个构成材料的分数的算法的同时进行计算。 可以映射和评估一系列像素的一系列偏转。

公开(公告)号：US20050227380A1

公开(公告)日：2005-10-13

申请号：US10815418

申请日：2004-04-01

申请人： Ronald Filippi ,  Lynne Gignac ,  Vincent McGahay ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Lynne Gignac ,  Vincent McGahay ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

IPC分类号： G06F13/28

CPC分类号： G01R31/2881

摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

摘要翻译： 公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。 在结构中感兴趣的位置确定菌株。 在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。 基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。 可以根据结果进行预测和设计更改。

公开(公告)号：US06812143B2

公开(公告)日：2004-11-02

申请号：US10279057

申请日：2002-10-24

申请人： Michael Lane ,  Fenton Read McFeely ,  Conal Murray ,  Robert Rosenberg

发明人： Michael Lane ,  Fenton Read McFeely ,  Conal Murray ,  Robert Rosenberg

IPC分类号： H01L2144

CPC分类号： H01L21/32051 ,  H01L21/76846 ,  H01L21/76871 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The barrier material of the invention provides for the electrodeposition of copper. The barrier layer includes a dielectric interface surface region, and a copper interface surface region with at least 50 atom percent of a copper interface metal. In particular, the barrier layer of the invention provides for the electrodeposition of copper or copper alloy directly onto the copper interface region of the barrier layer in a direct electrodeposition process. The process includes providing a dielectric layer disposed on an underlayer, contacting a barrier layer to the dielectric layer, and depositing a conducting layer onto the barrier layer.

摘要翻译： 本发明的阻挡材料提供铜的电沉积。 阻挡层包括介电界面表面区域和具有至少50原子百分比的铜界面金属的铜界面表面区域。 特别地，本发明的阻挡层提供在直接电沉积工艺中将铜或铜合金直接电沉积在阻挡层的铜界面区域上。 该方法包括提供设置在底层上的电介质层，使阻挡层与电介质层接触，并将导电层沉积在阻挡层上。