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    Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures
    1.
    发明申请
    Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures 失效
    具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法

    公开(公告)号：US20070235833A1

    公开(公告)日：2007-10-11

    申请号：US11393142

    申请日：2006-03-30

    申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    IPC分类号： H01L29/00

    CPC分类号： H01L27/10841 ,  H01L27/10864

    摘要： Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.

    摘要翻译： 具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法。 半导体结构包括限定在与沟槽的侧壁相邻的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。 半导体材料的中间区域分离第一和第二掺杂区域。 第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。 第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。 用于形成掺杂区域的方法包括沉积掺杂有掺杂剂或不同层的材料的层，每个掺杂剂或不同的层在沟槽中掺杂有一种掺杂剂，然后将掺杂剂从层或层扩散到与沟槽接壤的半导体材料 侧壁。

    Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer
    2.
    发明申请
    Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
    具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上

    公开(公告)号：US20070210890A1

    公开(公告)日：2007-09-13

    申请号：US11372387

    申请日：2006-03-09

    申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

    发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

    IPC分类号： H01H85/04

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  Y10T29/49107 ,  H01L2924/00

    摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.

    摘要翻译： 本发明提供一种用于集成电路的电子熔断器及其制造方法。 电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。 保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。 制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。 电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

    Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates
    4.
    发明申请
    Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates 失效

    公开(公告)号：US20060284250A1

    公开(公告)日：2006-12-21

    申请号：US11154906

    申请日：2005-06-16

    申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti

    发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L27/01

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/045

    摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.

    Storage Elements with Disguised Configurations and Methods of Using the Same
    6.
    发明申请
    Storage Elements with Disguised Configurations and Methods of Using the Same 审中-公开
    具有伪装配置的存储元件及其使用方法

    公开(公告)号：US20080067608A1

    公开(公告)日：2008-03-20

    申请号：US11928663

    申请日：2007-10-30

    申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

    发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

    IPC分类号： H01L27/06

    CPC分类号： H01L23/585 ,  H01L23/5256 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a gate region of the MOSFET; and (3) an implanted region coupled to the source/drain diffusion regions of the MOSFET such that a path between the source/drain diffusion regions functions as a short circuit or an open circuit. In another aspect, a design structure embodied in a machine readable medium for designing manufacturing, or testing a design is provided. Numerous other aspects are provided.

    摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是具有（1）具有源极/漏极扩散区域的金属氧化物半导体场效应晶体管（MOSFET）的集成电路（IC）的元件; （2）耦合到所述MOSFET的电熔丝（eFuse），使得所述eFuse的一部分用作所述MOSFET的栅极区域; 和（3）耦合到MOSFET的源极/漏极扩散区域的注入区域，使得源极/漏极扩散区域之间的路径用作短路或开路。 在另一方面，提供了体现在用于设计制造的机器可读介质或测试设计中的设计结构。 提供了许多其他方面。

    SEMICONDUCTOR FINFET STRUCTURES WITH ENCAPSULATED GATE ELECTRODES AND METHODS FOR FORMING SUCH SEMICONDUCTOR FINFET STRUCTURES
    8.
    发明申请
    SEMICONDUCTOR FINFET STRUCTURES WITH ENCAPSULATED GATE ELECTRODES AND METHODS FOR FORMING SUCH SEMICONDUCTOR FINFET STRUCTURES 有权
    具有封装栅极电极的半导体FINFET结构及其形成这种半导体FINFET结构的方法

    公开(公告)号：US20080048268A1

    公开(公告)日：2008-02-28

    申请号：US11923717

    申请日：2007-10-25

    申请人： Louis Hsu ,  Jack Mandelman

    发明人： Louis Hsu ,  Jack Mandelman

    IPC分类号： H01L29/76

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated from the process that dopes the fin body to form the source/drain regions. The sidewalls of the gate electrode are covered by sidewall spacers that are formed on the gate electrode but not on the sidewall of the fin body.

    摘要翻译： 其中FinFET的栅极被从引入掺杂剂的工艺掩模到FinFET的鳍状体中以形成源极/漏极区域的半导体结构以及制造这种半导体结构的方法。 栅极掺杂以及因此栅电极的功函数有利地与掺杂鳍体以形成源极/漏极区的过程隔离。 栅电极的侧壁由形成在栅电极上但不在鳍体的侧壁上的侧壁间隔物覆盖。

    BODY-CONTACTED SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SUCH BODY-CONTACTED SEMICONDUCTOR STRUCTURES
    9.
    发明申请
    BODY-CONTACTED SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SUCH BODY-CONTACTED SEMICONDUCTOR STRUCTURES 失效
    人体接触半导体结构和制造这种接触式半导体结构的方法

    公开(公告)号：US20080044959A1

    公开(公告)日：2008-02-21

    申请号：US11925352

    申请日：2007-10-26

    申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    IPC分类号： H01L21/86

    CPC分类号： H01L21/84 ,  H01L27/0218 ,  H01L27/10841 ,  H01L27/1203 ,  H01L29/66545

    摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.

    摘要翻译： 一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括建立在绝缘体上半导体（SOI）晶片上的多个垂直存储单元和SOI晶片的埋入介质层中的体接触。 体接触将半导体本体与一个垂直存储单元的存取器件的沟道区和SOI晶片的半导体衬底电耦合。 身体接触提供了一种电流泄漏路径，可减少浮体对垂直记忆体的影响。 体接触可以通过离子注入工艺形成，该方法改变掩埋介电层的区域的化学计量，使得改性区域以相对较高的电阻变为导电性。

    A REAL-TIME ADAPTIVE SRAM ARRAY FOR HIGH SEU IMMUNITY
    10.
    发明申请
    A REAL-TIME ADAPTIVE SRAM ARRAY FOR HIGH SEU IMMUNITY 有权
    实时自适应SRAM阵列高SEU免疫

    公开(公告)号：US20070211527A1

    公开(公告)日：2007-09-13

    申请号：US11308215

    申请日：2006-03-13

    申请人： Louis Hsu ,  Jack Mandelman ,  Robert Wong ,  Chih-Chao Yang

    发明人： Louis Hsu ,  Jack Mandelman ,  Robert Wong ,  Chih-Chao Yang

    IPC分类号： G11C16/04

    CPC分类号： G11C11/4125

    摘要： A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.

    摘要翻译： 一种用于自动调整存储器件（例如SRAM阵列）中的一个或多个电参数的系统和方法。 该系统和方法实现SRAM感测子阵列，用于加速收集故障率数据，用于确定单个事件不起作息和主SRAM阵列性能之间的最佳权衡的操作点。 将加速失败率数据输入到在电离粒子环境中将初级SRAM存储器阵列的SEU灵敏度设定为预定故障率的算法。 为了提供符合最佳性能的SEU的免疫力，实时地维持预定的故障率。