公开(公告)号：US6121827A

公开(公告)日：2000-09-19

申请号：US293510

申请日：1999-04-15

申请人： Ramin Khoini-Poorfard ,  Lysander B. Lim

发明人： Ramin Khoini-Poorfard ,  Lysander B. Lim

IPC分类号： H01L23/50 ,  H01L25/00

CPC分类号： H01L23/50 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6688 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/3025

摘要： A mixed signal integrated circuit board having decreased sensitivity of analog circuitry to digital circuitry noise is disclosed. In the mixed-signal integrated board of the present invention, a new (second) analog ground is created. This new analog ground is not limited by the manufacturing specification of connectivity to the substrate of the circuit board and is thereby free of transient noise generated by digital components on the board. In a mixed-signal integrated circuit board of the present invention, the new analog ground becomes the preferred ground and is utilized in many sensitive analog applications including voltage and current measurements. The new analog ground is easy to create as it does not involved complicated circuitry. The new analog ground may be created even after the initial circuit schematics has been created.

摘要翻译： 公开了一种具有降低的模拟电路对数字电路噪声灵敏度的混合信号集成电路板。 在本发明的混合信号集成电路板中，产生新的（第二）模拟地。 这种新的模拟接地不受电路板基板的连接的制造规范的限制，从而不受板上数字部件产生的瞬态噪声的影响。 在本发明的混合信号集成电路板中，新的模拟地被成为优选的地面，并被用于包括电压和电流测量在内的许多敏感的模拟应用中。 新的模拟地线容易创建，因为它不涉及复杂的电路。 即使在创建初始电路原理图之后，也可能会创建新的模拟地。

公开(公告)号：US5841382A

公开(公告)日：1998-11-24

申请号：US820819

申请日：1997-03-19

申请人： Robert W. Walden ,  Ramin Khoini-Poorfard ,  William E. Burchanowski

发明人： Robert W. Walden ,  Ramin Khoini-Poorfard ,  William E. Burchanowski

IPC分类号： H03M1/10 ,  H03M1/68 ,  H03M1/76

CPC分类号： H03M1/109 ,  H03M1/685 ,  H03M1/765

摘要： Testing of digital-to-analog converters is accelerated by applying one or more different approaches. One approach relies on a switched capacitor, which lowers the overall capacitance of the converter during testing, thereby reducing the settling time for each code value. Another approach makes the duration of each testing step a function of the particular code value, rather than using the worst-case settling time for each testing step. Yet another approach uses a sequence of non-consecutive code values to determine whether each switch in the converter is functional. Using non-consecutive code values permits the use of partial settling times during converter testing. Each of the approaches can be used to accelerate the testing of D/A converters, whether they have linear or folded resistor strings.

摘要翻译： 通过应用一种或多种不同的方法来加速数模转换器的测试。 一种方法依赖于开关电容器，其在测试期间降低转换器的总体电容，从而减少每个代码值的建立时间。 另一种方法使得每个测试步骤的持续时间是特定代码值的函数，而不是使用每个测试步骤的最坏情况建立时间。 另一种方法使用非连续代码值序列来确定转换器中的每个开关是否功能。 使用非连续代码值允许在转换器测试期间使用部分建立时间。 可以使用每种方法来加速D / A转换器的测试，无论它们是线性还是折叠电阻串。

公开(公告)号：US09036091B2

公开(公告)日：2015-05-19

申请号：US12986053

申请日：2011-01-06

申请人： Alan F. Hendrickson ,  Alessandro Piovaccari ,  Ramin Khoini-Poorfard ,  Mitchell Reid ,  Frederick Alan Rush ,  Jean-Marc Guyot ,  David Le Goff ,  Michael Robert May ,  Henry William Singor ,  Qi Cai ,  Peter Jozef Vancorenland ,  Chunyu Xin ,  Pascal Blouin

发明人： Alan F. Hendrickson ,  Alessandro Piovaccari ,  Ramin Khoini-Poorfard ,  Mitchell Reid ,  Frederick Alan Rush ,  Jean-Marc Guyot ,  David Le Goff ,  Michael Robert May ,  Henry William Singor ,  Qi Cai ,  Peter Jozef Vancorenland ,  Chunyu Xin ,  Pascal Blouin

IPC分类号： H04N5/44 ,  H04N5/50 ,  H04N21/426 ,  H04N5/46 ,  H03J1/00

CPC分类号： H04N21/42638 ,  H03J1/0008 ,  H04N5/46

摘要： An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.

摘要翻译： 集成电路包括调谐器，数字电视（DTV）解调器，模拟电视（ATV）解调器和控制器。 调谐器包括用于接收包括模拟电视信号和数字电视信号中的至少一个的射频（RF）信号的输入，并且包括第一输出端和第二输出端。 DTV解调器包括耦合到调谐器的第一输出端的DTV输入，并且包括DTV输出端。 ATV解调器包括耦合到调谐器的第二输出端子的ATV输入并且包括ATV输出端子。 控制器耦合到调谐器，DTV解调器和ATV解调器，以配置调谐器和至少一个DTV解调器和ATV解调器，用于以选定的电视格式接收电视内容。

公开(公告)号：US08848110B2

公开(公告)日：2014-09-30

申请号：US12790405

申请日：2010-05-28

申请人： Ramin Khoini-Poorfard ,  Alan F. Hendrickson ,  Alessandro Piovaccari ,  David S. Trager ,  Aslamali A. Rafi ,  Abdulkerim L. Coban ,  David Le Goff

发明人： Ramin Khoini-Poorfard ,  Alan F. Hendrickson ,  Alessandro Piovaccari ,  David S. Trager ,  Aslamali A. Rafi ,  Abdulkerim L. Coban ,  David Le Goff

IPC分类号： H04N5/52 ,  H04N5/44 ,  H04L27/02 ,  H03G3/30 ,  H04N5/455 ,  H03G3/00 ,  H04L27/00 ,  H04L27/08 ,  H04N5/04

CPC分类号： H04N5/455 ,  H03G3/001 ,  H03G3/002 ,  H03G3/3068 ,  H04L27/0002 ,  H04L27/02 ,  H04L27/08 ,  H04N5/04 ,  H04N5/52

摘要： A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.

摘要翻译： 接收机电路包括模拟前端和数字处理单元。 模拟前端包括用于接收射频（RF）信号的输入，用于接收增益调整信号的第一控制输入，用于接收定时信号的第二控制输入和用于提供数字中频的信号输出（ IF）信号。 模拟前端根据增益调整信号更新多个增益级的增益并与定时信号同步。 数字处理单元被配置为产生从数字IF信号导出的至少一个输出信号。 数字处理单元包括定时恢复电路，其被配置为基于数字IF信号生成定时信号，以控制多个可调增益级中的每一个的更新增益的定时。

公开(公告)号：US08611844B2

公开(公告)日：2013-12-17

申请号：US13344227

申请日：2012-01-05

申请人： Yu Su ,  Mustafa H. Koroglu ,  Abhishek Kammula ,  Ramin Khoini-Poorfard

发明人： Yu Su ,  Mustafa H. Koroglu ,  Abhishek Kammula ,  Ramin Khoini-Poorfard

IPC分类号： H04B1/16

CPC分类号： H04N5/455 ,  H04B1/18 ,  H04H40/27 ,  H04N21/42607 ,  H04N21/6112 ,  H04N21/6118

摘要： A low noise amplifier (LNA) for use in a receiver circuit includes an adjustable impedance network including an input for receiving a radio frequency signal, a plurality of control inputs, and an output. The LNA further includes a controller coupled to the plurality of control inputs and configured to control an impedance of the adjustable impedance network. The controller controls the adjustable impedance network to provide a relatively low impedance in a terrestrial mode and to provide a relatively high impedance in a cable mode.

摘要翻译： 用于接收器电路的低噪声放大器（LNA）包括可调阻抗网络，其包括用于接收射频信号的输入，多个控制输入和输出。 LNA还包括耦合到多个控制输入并被配置为控制可调阻抗网络的阻抗的控制器。 控制器控制可调阻抗网络以在地面模式中提供相对较低的阻抗并且在电缆模式中提供相对较高的阻抗。

公开(公告)号：US20130279636A1

公开(公告)日：2013-10-24

申请号：US13923824

申请日：2013-06-21

申请人： Ramin Khoini-Poorfard ,  Alessandro Piovaccari ,  Aslamali A. Rafi ,  Mustafa H. Koroglu ,  David S. Trager ,  Abdulkerim L. Coban

发明人： Ramin Khoini-Poorfard ,  Alessandro Piovaccari ,  Aslamali A. Rafi ,  Mustafa H. Koroglu ,  David S. Trager ,  Abdulkerim L. Coban

IPC分类号： H04B1/28

CPC分类号： H04B1/28 ,  H03H11/04 ,  H04B1/30 ,  H04L27/148 ,  H04N5/455 ,  H04N5/50

摘要： A receiver includes an input section, a plurality of RF sections, an output circuit, and a controller. The input section receives and amplifies a radio frequency (RF) input signal to provide an amplified RF signal, and has a gain input. The plurality of RF sections each have an input for receiving the amplified RF signal, and an output for providing an intermediate frequency signal. The output circuit provides an intermediate frequency output signal in response to an output of at least one of the plurality of RF sections. The controller has an output coupled to the gain input of the input section.

摘要翻译： 接收机包括输入部分，多个RF部分，输出电路和控制器。 输入部分接收和放大射频（RF）输入信号以提供放大的RF信号，并具有增益输入。 多个RF部分各自具有用于接收放大的RF信号的输入端和用于提供中频信号的输出端。 输出电路响应于多个RF部分中的至少一个的输出而提供中频输出信号。 控制器具有耦合到输入部分的增益输入的输出。

公开(公告)号：US20120176550A1

公开(公告)日：2012-07-12

申请号：US12986053

申请日：2011-01-06

申请人： Alan F. Hendrickson ,  Alessandro Piovaccari ,  Ramin Khoini-Poorfard ,  Mitchell Reid ,  Frederick Alan Rush ,  Jean-Marc Guyot ,  David Le Goff ,  Michael Robert May ,  Henry William Singor ,  Qi Cai ,  Peter Jozef Vancorenland ,  Chunyu Xin ,  Pascal Blouin

发明人： Alan F. Hendrickson ,  Alessandro Piovaccari ,  Ramin Khoini-Poorfard ,  Mitchell Reid ,  Frederick Alan Rush ,  Jean-Marc Guyot ,  David Le Goff ,  Michael Robert May ,  Henry William Singor ,  Qi Cai ,  Peter Jozef Vancorenland ,  Chunyu Xin ,  Pascal Blouin

IPC分类号： H04N5/455

CPC分类号： H04N21/42638 ,  H03J1/0008 ,  H04N5/46

摘要： An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.

摘要翻译： 集成电路包括调谐器，数字电视（DTV）解调器，模拟电视（ATV）解调器和控制器。 调谐器包括用于接收包括模拟电视信号和数字电视信号中的至少一个的射频（RF）信号的输入，并且包括第一输出端和第二输出端。 DTV解调器包括耦合到调谐器的第一输出端的DTV输入，并且包括DTV输出端。 ATV解调器包括耦合到调谐器的第二输出端子的ATV输入并且包括ATV输出端子。 控制器耦合到调谐器，DTV解调器和ATV解调器，以配置调谐器和至少一个DTV解调器和ATV解调器，用于以选定的电视格式接收电视内容。

公开(公告)号：US08145172B2

公开(公告)日：2012-03-27

申请号：US12277866

申请日：2008-11-25

申请人： Ramin Khoini-Poorfard ,  Alessandro Piovaccari ,  Aslamali A. Rafi ,  Mustafa H. Koroglu ,  David S. Trager

发明人： Ramin Khoini-Poorfard ,  Alessandro Piovaccari ,  Aslamali A. Rafi ,  Mustafa H. Koroglu ,  David S. Trager

IPC分类号： H04B1/06

CPC分类号： H03J1/0008 ,  H03J2200/10 ,  H03J2200/32

摘要： A receiver (400) includes a tracking bandpass filter (420) and a signal processing circuit (430-480). The tracking bandpass filter (420) has a first input for receiving a radio frequency (RF) signal, and an output, and includes a first portion (731) on a semiconductor die (730), and at least one inductor (721). The at least one inductor (721) is operatively coupled to the first portion of the tracking bandpass filter (420). The signal processing circuit (430-480) has an input coupled to the output of the tracking bandpass filter (420), and an output for providing a processed signal. The semiconductor die (730) and the at least one inductor (721) are integrated into a single multi-chip module (MCM) (710).

摘要翻译： 接收器（400）包括跟踪带通滤波器（420）和信号处理电路（430-480）。 跟踪带通滤波器（420）具有用于接收射频（RF）信号的第一输入和输出，并且包括半导体管芯（730）上的第一部分（731）和至少一个电感器（721）。 至少一个电感器（721）可操作地耦合到跟踪带通滤波器（420）的第一部分。 信号处理电路（430-480）具有耦合到跟踪带通滤波器（420）的输出的输入端和用于提供处理信号的输出端。 半导体管芯（730）和至少一个电感器（721）被集成到单个多芯片模块（MCM）（710）中。

公开(公告)号：US07904040B2

公开(公告)日：2011-03-08

申请号：US12004006

申请日：2007-12-19

申请人： Ramin Khoini-Poorfard ,  Andrew W. Krone

发明人： Ramin Khoini-Poorfard ,  Andrew W. Krone

IPC分类号： H04B7/08

CPC分类号： H04N5/4446 ,  H03D3/006 ,  H03D3/007 ,  H03L7/18 ,  H04H40/90 ,  H04N5/4401 ,  H04N5/50 ,  H04N7/20 ,  H04N21/4263

摘要： Receiver architectures and associated methods are disclosed that provide initial analog coarse tuning of desired channels within a received signal spectrum, such as a set-top box signal spectrum for satellite communications. These architectures provide significant advantages over prior direct down-conversion (DDC) architectures and low intermediate-frequency (IF) architectures, particularly where two tuners are desired on the same integrated circuit. Rather than using a low-IF frequency or directly converting the desired channel frequency to DC, initial coarse tuning provided by analog coarse tuning circuitry allows for a conversion to a frequency range around DC. This coarse tuning circuitry can be implemented, for example, using a large-step local oscillator (LO) that provides a coarse tune analog mixing signal. Once mixed down, the desired channel may then be fine-tuned through digital processing, such as through the use of a wide-band analog-to-digital converter (ADC) or a narrow-band tunable bandpass ADC.

摘要翻译： 公开了接收机架构和相关方法，其提供接收信号频谱内的期望信道的初始模拟粗调，例如用于卫星通信的机顶盒信号频谱。 这些架构与先前的直接下变频（DDC）架构和低中频（IF）架构相比具有显着的优势，特别是在同一集成电路上需要两个调谐器的情况下。 不是使用低IF频率或直接将期望的信道频率转换为DC，而是由模拟粗调谐电路提供的初始粗调调可以转换到大约DC的频率范围。 该粗调谐电路可以例如使用提供粗调模拟混频信号的大步本地振荡器（LO）来实现。 一旦混合，则可以通过数字处理（例如通过使用宽带模数转换器（ADC）或窄带可调谐带通ADC）来微调所需的信道。

公开(公告)号：US06909390B2

公开(公告)日：2005-06-21

申请号：US10670160

申请日：2003-09-23

申请人： Ramin Khoini-Poorfard ,  Douglas R. Frey

发明人： Ramin Khoini-Poorfard ,  Douglas R. Frey

IPC分类号： H03M1/06 ,  H03M1/08 ,  H03M1/66

CPC分类号： H03M1/0678 ,  H03M1/0863 ,  H03M1/66

摘要： A digital-to-analog converter circuit for a subscriber line analog front end includes a differential amplifier, switch circuitry, and first and second current steering digital-to-analog converters (DAC), each DAC having a first and second output forming a differential DAC output. The switch circuitry couples the differential output of at most a selected one of the first and second DACs to a pair of switch nodes. When the differential output of the selected DAC is coupled to the pair of switch nodes, the differential output of the other DAC is shorted. A differential input of the differential amplifier is communicatively coupled to the pair of switch nodes. A differential output of the differential amplifier is coupled to drive a tip line and a ring line of a subscriber line. In various embodiments, the DACs, switch circuitry, and differential amplifier reside on the same semiconductor substrate.

摘要翻译： 用于用户线模拟前端的数模转换器电路包括差分放大器，开关电路和第一和第二电流转向数模转换器（DAC），每个DAC具有形成差分的第一和第二输出 DAC输出。 开关电路将至少一个第一和第二DAC中的一个的差分输出耦合到一对开关节点。 当所选DAC的差分输出耦合到该对开关节点时，另一DAC的差分输出短路。 差分放大器的差分输入通信地耦合到该对交换节点。 差分放大器的差分输出被耦合以驱动用户线的尖端线和环线。 在各种实施例中，DAC，开关电路和差分放大器驻留在相同的半导体衬底上。