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42 条记录 (耗时 0.029 秒)

    Landscaping tow apparatus
    23.
    发明授权
    Landscaping tow apparatus 有权

    公开(公告)号：US10375873B2

    公开(公告)日：2019-08-13

    申请号：US15053390

    申请日：2016-02-25

    申请人： Brian Campbell

    发明人： Brian Campbell

    IPC分类号： A01B49/02 ,  A01B63/22 ,  A01B63/24

    摘要： A landscaping tow apparatus for cultivating dirt or land. The apparatus includes a U-shaped bracket rotatably secured to a tool head support, wherein the tool head support includes a plurality of tool heads removably secured thereon for cultivating the land. A hitch is further affixed to the U-shaped bracket and can mount the apparatus to a vehicle, such as a tractor or riding lawnmower. A pair of wheels are extendable from the bracket in order to engage the ground and lift the tool head support for rotation thereof. In operation, the hitch is secured to a tractor and the side of the tool head support having the desired tool head is positioned against the ground. The wheels are extended so that the tool head support can be rotated in order to have a different tool head engage the ground.

    Data storage system having memory controller with embedded CPU
    27.
    发明申请
    Data storage system having memory controller with embedded CPU 审中-公开
    具有嵌入式CPU的存储控制器的数据存储系统

    公开(公告)号：US20060236032A1

    公开(公告)日：2006-10-19

    申请号：US11105265

    申请日：2005-04-13

    申请人： Brian Campbell ,  Brian Magnuson ,  Ofer Porat ,  David Scheffey ,  Clayton Curry

    发明人： Brian Campbell ,  Brian Magnuson ,  Ofer Porat ,  David Scheffey ,  Clayton Curry

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0866 ,  G06F2212/261

    摘要： A memory system includes a bank of memory, an interface to a packet switching network, and a memory controller. The memory system is adapted to receive by the interface a packet based command to access the bank of memory. The memory controller is adapted to execute initialization and configuration cycles for the bank of memory. An embedded central processing unit (CPU) is included in the memory controller and is adapted to execute computer executable instructions. The memory controller is adapted to process the packet based command.

    摘要翻译： 存储器系统包括一组存储器，到分组交换网络的接口和存储器控制器。 存储器系统适于由接口接收基于分组的命令来访问存储器组。 存储器控制器适于对存储器组执行初始化和配置周期。 嵌入式中央处理单元（CPU）包括在存储器控制器中并且适于执行计算机可执行指令。 存储器控制器适于处理基于分组的命令。

    High-fanin static multiplexer
    28.
    发明申请
    High-fanin static multiplexer 失效
    高扇静态多路复用器

    公开(公告)号：US20050225359A1

    公开(公告)日：2005-10-13

    申请号：US10821575

    申请日：2004-04-09

    申请人： Brian Campbell

    发明人： Brian Campbell

    IPC分类号： H03K17/693 ,  H03K19/094

    CPC分类号： H03K17/693

    摘要： An improved high-fanin multiplexer that is highly-scalable, fast and area-efficient. In one embodiment of the present invention, multiple logic “legs” are attached to a common output line. Each leg comprises one pMOS pull-up transistor and one nMOS pull-down transistor. The gate of the pMOS transistor in each leg is connected to the output of an And-Or-Invert (AOI) gate whose inputs are connected to a plurality of select lines and a plurality of data lines. The gate of the nMOS transistor in each leg is connected to the output of an Or-And-Invert (OAI) gate whose inputs are connected to a plurality of select lines (the logical complements of the select lines for the AOI), and a plurality of data input lines. The high-fanin multiplexer of the present invention offers numerous advantages over the prior art. In particular, the high-fanin multiplexer of the present invention has very small self-loading allowing a large number of inputs while also maintaining a high fan out speed. In addition, the small input capacitive load allows the driving gates to be small, thereby conversing surface area within an integrated circuit.

    摘要翻译： 高度可扩展的，高速度，高效率的高分辨率多路复用器。 在本发明的一个实施例中，多个逻辑“腿”附接到公共输出线。 每条支路包括一个pMOS上拉晶体管和一个nMOS下拉晶体管。 每条支路中的pMOS晶体管的栅极连接到其输入连接到多条选择线和多条数据线的“和”或“反”（AOI）门的输出。 每条支路中的nMOS晶体管的栅极连接到其输入连接到多条选择线（AOI的选择线的逻辑补码）的Or-And-Invert（OAI）门的输出端， 多条数据输入线。 与现有技术相比，本发明的高扇区多路复用器提供了许多优点。 特别地，本发明的高扇区多路复用器具有非常小的自负载，允许大量的输入，同时还保持高的扇出速度。 此外，小的输入电容性负载允许驱动门较小，从而在集成电路内转换表面积。