公开(公告)号：US20190237147A1

公开(公告)日：2019-08-01

申请号：US16231402

申请日：2018-12-22

Applicant: Winbond Electronics Corp.

Inventor： Hiroki Murakami

IPC: G11C16/30 ,  G11C16/14 ,  H02M3/07 ,  G11C16/08

Abstract: A voltage generation circuit, having a circuit scale significantly reduced as compared with the related art, is provided. The voltage generation circuit of the disclosure includes a charge pump outputting a boosted voltage to an output node, a resistor connected between the output node and another output node, and a current source circuit having first and second current paths connected in parallel between the another output node and a reference potential. The first current path includes a resistor and a first DAC. The first DAC generates a first constant current corresponding to a voltage generation code. The second current path includes a second DAC. The second DAC generates a second constant current corresponding to a code obtained by inverting the voltage generation code. Thereby, a driving voltage obtained by lowering the boosted voltage is generated at the other output node.

公开(公告)号：US09865358B2

公开(公告)日：2018-01-09

申请号：US15435985

申请日：2017-02-17

Applicant: Winbond Electronics Corp.

Inventor： Hiroki Murakami ,  Kenichi Arakawa

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/3445 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: Provided is a flash memory device capable of restricting power consumption in an erase operation. The invention includes a plurality of wells, a power supply device, and a coupling device. The power supply device applies erase voltages to the wells for performing an erase operation. The coupling device performs selective coupling between the wells. When performing the erase operation on the wells, the power supply device applies the erase voltage to one of the wells, and applies the erase voltage to the other one of the wells after the coupling device electrically couples the one of the wells to the other one of the wells.

公开(公告)号：US20170365351A1

公开(公告)日：2017-12-21

申请号：US15611791

申请日：2017-06-02

Applicant: Winbond Electronics Corp.

Inventor： Hiroki Murakami ,  Makoto Senoo

IPC: G11C16/32 ,  G11C16/26 ,  G11C16/14

CPC classification number: G11C16/32 ,  G11C5/066 ,  G11C7/1066 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C2207/108

Abstract: A voltage generating circuit 100 of the present invention includes a control logic 110, a voltage generating element 120 and a connecting element 130. The voltage generating element 120 includes a plurality of registers A-1, B-1, C-1, D-1, voltage generating blocks A-2, B-2, C-2 and a voltage switch 32. The registers A-1, B-1, C-1, D-1 hold data provided from control logic 110. The voltage generating blocks A-2, B-2, C-2 generate voltage based on voltage control data held by the registers A-1, B-1, C-1. The voltage switch 32 selects voltages based on selection control data held by the register D-1. The connecting element 130 includes signal lines for sequentially transmitting the voltage control data or the selection control data, signal lines for sequentially transmitting a clock signal CLK and signal lines for controlling output of data held by the registers.

公开(公告)号：US09449704B2

公开(公告)日：2016-09-20

申请号：US14689055

申请日：2015-04-17

Applicant: Winbond Electronics Corp.

Inventor： Hiroki Murakami

IPC: G11C16/32 ,  G11C7/22 ,  G11C16/04

CPC classification number: G11C16/32 ,  G11C7/222 ,  G11C16/0483

Abstract: A flash memory, a memory module, a computer-readable recording medium and an operating method are provided, which can perform a flexible setup by a flexible clock scheme. A NAND-type flash memory 100 of the invention includes: a memory array 110 having NAND-type memory cells, a controller 150 including a processor and a ROM/RAM, and a system clock generating circuit 200 configured to generate an internal system clock signal. The ROM/RAM is at least stored with setup commands for a setup of the flash memory, and the processor processes the setup commands based on the internal system clock signal during a setup period. The controller 150 further controls the system clock generating circuit 200, so that a frequency of the internal system clock signal becomes high speed during the setup period.

Abstract translation: 提供了闪存，存储器模块，计算机可读记录介质和操作方法，其可以通过灵活的时钟方案执行灵活的设置。 本发明的NAND型闪存100包括：具有NAND型存储单元的存储器阵列110，包括处理器和ROM / RAM的控制器150以及被配置为产生内部系统时钟信号的系统时钟产生电路200 。 至少存储ROM / RAM用于设置闪速存储器的设置命令，并且处理器在设置期间基于内部系统时钟信号处理设置命令。 控制器150进一步控制系统时钟产生电路200，使得内部系统时钟信号的频率在建立期间变为高速。

公开(公告)号：US09317053B2

公开(公告)日：2016-04-19

申请号：US14263536

申请日：2014-04-28

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano ,  Hiroki Murakami

IPC: H01L29/8605 ,  H01L27/08 ,  G05F1/575 ,  H01L49/02

CPC classification number: G05F1/575 ,  H01L27/0802 ,  H01L28/20

Abstract: The invention provides a voltage regulator. The voltage regulator (100) of the invention includes a comparison circuit (20) and a voltage divider circuit (110). The voltage divider circuit (110) has a PMOS transistor (T6) connected to a voltage source (VDD) and resistors (R1, R2, R3, R4, R5 and R6) serially connected between the transistor (T6) and a reference voltage. A feedback voltage generated from a node (N3) between resistors R4 and R5 is provided to the comparison circuit (20). In addition, a middle voltage (Vm) generated from a node (Nc) of the resistors is provided to a well region, so the parasitic capacitance is reduced.

Abstract translation: 本发明提供一种电压调节器。 本发明的电压调节器（100）包括比较电路（20）和分压电路（110）。 分压器电路（110）具有连接到电压源（VDD）的PMOS晶体管（T6）和串联连接在晶体管（T6）和参考电压之间的电阻器（R1，R2，R3，R4，R5和R6）。 从电阻器R4和R5之间的节点（N3）产生的反馈电压被提供给比较电路（20）。 此外，从电阻器的节点（Nc）产生的中间电压（Vm）被提供给阱区域，因此寄生电容减小。

公开(公告)号：US20160071610A1

公开(公告)日：2016-03-10

申请号：US14689055

申请日：2015-04-17

Applicant: Winbond Electronics Corp.

Inventor： Hiroki Murakami

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G11C7/222 ,  G11C16/0483

Abstract: A flash memory, a memory module, a computer-readable recording medium and an operating method are provided, which can perform a flexible setup by a flexible clock scheme. A NAND-type flash memory 100 of the invention includes: a memory array 110 having NAND-type memory cells, a controller 150 including a processor and a ROM/RAM, and a system clock generating circuit 200 configured to generate an internal system clock signal. The ROM/RAM is at least stored with setup commands for a setup of the flash memory, and the processor processes the setup commands based on the internal system clock signal during a setup period. The controller 150 further controls the system clock generating circuit 200, so that a frequency of the internal system clock signal becomes high speed during the setup period.

Abstract translation: 提供了闪存，存储器模块，计算机可读记录介质和操作方法，其可以通过灵活的时钟方案执行灵活的设置。 本发明的NAND型闪存100包括：具有NAND型存储单元的存储器阵列110，包括处理器和ROM / RAM的控制器150以及被配置为产生内部系统时钟信号的系统时钟产生电路200 。 至少存储ROM / RAM用于设置闪速存储器的设置命令，并且处理器在设置期间基于内部系统时钟信号处理设置命令。 控制器150进一步控制系统时钟产生电路200，使得内部系统时钟信号的频率在建立期间变为高速。

公开(公告)号：US08963624B2

公开(公告)日：2015-02-24

申请号：US13966023

申请日：2013-08-13

Applicant: Winbond Electronics Corp.

Inventor： Hiroki Murakami

IPC: G11C7/12 ,  G05F1/46 ,  H02M3/07

CPC classification number: G05F1/465 ,  G11C7/12 ,  H02M3/073

Abstract: A boosting circuit, includes an output circuit including a first transmission circuit, transmitting charges of a first boosting node to a first output node according to a first transmission control signal, a detection circuit, detecting the voltage level of the first output node, and a pre-charge circuit pre-charging the first boosting node according a detection signal of the detection circuit; a first pump circuit includes a second transmission circuit, transmitting charges to a second output node according to a second transmission control signal, and a first capacitance unit, coupled to the first boosting node, boosting the voltage level of the first boosting node according to charges transmitted in the second output node; and a control circuit, coupled to the output circuit and the first pump circuit, controls the second transmission control signal according to the voltage level of the first output node.

Abstract translation: 升压电路包括：输出电路，包括第一发送电路，根据第一发送控制信号向第一输出节点发送第一升压节点的电荷;检测电路，检测第一输出节点的电压电平;以及 预充电电路根据检测电路的检测信号对第一升压节点进行预充电; 第一泵电路包括第二传输电路，根据第二传输控制信号向第二输出节点传送电荷;第一电容单元，耦合到第一升压节点，根据电荷升高第一升压节点的电压电平 在第二输出节点中传送; 以及耦合到所述输出电路和所述第一泵电路的控制电路，根据所述第一输出节点的电压电平控制所述第二传输控制信号。