公开(公告)号：US20080108213A1

公开(公告)日：2008-05-08

申请号：US11654133

申请日：2007-01-17

申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L21/4763 ,  H01L21/3205

CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

公开(公告)号：US20060270138A1

公开(公告)日：2006-11-30

申请号：US11499946

申请日：2006-08-07

申请人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

发明人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

IPC分类号： H01L21/8238

CPC分类号： H01L29/66621 ,  H01L29/66553

摘要： A transistor includes a substrate and a device isolation layer that is formed on the substrate to define an active region. A gate pattern crosses over the active region. A gate insulation layer is interposed between the gate pattern and the active region. Source and drain regions are formed in the active region adjacent to respective sides of the gate pattern. A channel region is disposed in the active region between the source and drain regions. The channel region includes a recessed portion.

摘要翻译： 晶体管包括衬底和器件隔离层，其形成在衬底上以限定有源区。 栅极模式跨越有源区域。 栅极绝缘层插入在栅极图案和有源区域之间。 源极和漏极区域形成在与栅极图案的相应侧面相邻的有源区域中。 沟道区设置在源区和漏区之间的有源区中。 通道区域包括凹部。

公开(公告)号：US07141851B2

公开(公告)日：2006-11-28

申请号：US10922344

申请日：2004-08-20

申请人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

发明人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

IPC分类号： H01L29/78

CPC分类号： H01L29/66621 ,  H01L29/66553

摘要： A transistor includes a substrate and a device isolation layer that is formed on the substrate to define an active region. A gate pattern crosses over the active region. A gate insulation layer is interposed between the gate pattern and the active region. Source and drain regions are formed in the active region adjacent to respective sides of the gate pattern. A channel region is disposed in the active region between the source and drain regions. The channel region includes a recessed portion.

摘要翻译： 晶体管包括衬底和器件隔离层，其形成在衬底上以限定有源区。 栅极模式跨越有源区域。 栅极绝缘层插入在栅极图案和有源区域之间。 源极和漏极区域形成在与栅极图案的相应侧面相邻的有源区域中。 沟道区设置在源区和漏区之间的有源区中。 通道区域包括凹部。

公开(公告)号：US07960844B2

公开(公告)日：2011-06-14

申请号：US12499980

申请日：2009-07-09

申请人： Young-Chul Jang ,  Han-Soo Kim ,  Jae-Hun Jeong ,  Soon-Moon Jung

发明人： Young-Chul Jang ,  Han-Soo Kim ,  Jae-Hun Jeong ,  Soon-Moon Jung

IPC分类号： H01L23/48

CPC分类号： H01L27/11578 ,  H01L27/11524 ,  H01L27/11551 ,  H02J2007/0049

摘要： Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well.

摘要翻译： 公开了闪存装置和操作方法。 闪速存储器件包括底部存储单元阵列和设置在底部存储单元阵列上的顶部存储器单元阵列。 底部存储单元阵列包括底部半导体层，底部阱以及多个底部存储单元单元。 顶部存储单元阵列包括顶部半导体层，顶部阱以及多个顶部存储单元。 井顶偏置线设置在顶部存储单元阵列上，并且包括底部阱偏置线和顶部阱偏置线。底部阱偏置线电连接到底部阱，并且顶部阱偏置线电连接到 顶好

公开(公告)号：US20050040475A1

公开(公告)日：2005-02-24

申请号：US10922344

申请日：2004-08-20

申请人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

发明人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/84 ,  H01L31/062

CPC分类号： H01L29/66621 ,  H01L29/66553

摘要： A transistor includes a substrate and a device isolation layer that is formed on the substrate to define an active region. A gate pattern crosses over the active region. A gate insulation layer is interposed between the gate pattern and the active region. Source and drain regions are formed in the active region adjacent to respective sides of the gate pattern. A channel region is disposed in the active region between the source and drain regions. The channel region includes a recessed portion.

摘要翻译： 晶体管包括衬底和器件隔离层，其形成在衬底上以限定有源区。 栅极模式跨越有源区域。 栅极绝缘层插入在栅极图案和有源区域之间。 源极和漏极区域形成在与栅极图案的相应侧面相邻的有源区域中。 沟道区设置在源区和漏区之间的有源区中。 通道区域包括凹部。

公开(公告)号：US20070181170A1

公开(公告)日：2007-08-09

申请号：US11702612

申请日：2007-02-06

申请人： Kyoung-Ho Kim ,  Young-Chul Jang

发明人： Kyoung-Ho Kim ,  Young-Chul Jang

IPC分类号： B08B3/00 ,  B08B3/12 ,  B08B6/00

CPC分类号： H01L21/6715

摘要： An apparatus for supplying a solution to a substrate includes a nozzle unit. The nozzle unit may include at least one nozzle having a variable structure in which lateral portions of the at least one nozzle are bent toward a central portion of the at least one nozzle. Each nozzle of the nozzle unit may include a hinged connecting member disposed at the central portion of each of the nozzles. The hinge angles between lateral portions of each of the nozzles may vary during operation. Each of the nozzles may include a plurality of spray holes for uniformly providing a developing solution onto the photoresist film. Some of the plurality of holes positioned near the central portion of the nozzles may be substantially wider than some of the plurality of holes positioned near lateral portions of the nozzles.

摘要翻译： 用于将溶液供给到基板的装置包括喷嘴单元。 喷嘴单元可以包括具有可变结构的至少一个喷嘴，其中至少一个喷嘴的侧向部分朝向至少一个喷嘴的中心部分弯曲。 喷嘴单元的每个喷嘴可以包括设置在每个喷嘴的中心部分处的铰接连接构件。 每个喷嘴的横向部分之间的铰链角度可以在操作期间变化。 每个喷嘴可以包括用于均匀地将显影溶液提供到光致抗蚀剂膜上的多个喷射孔。 位于喷嘴的中心部分附近的多个孔中的一些孔可以比位于喷嘴的侧面部分附近的多个孔中的一些孔大得多。

公开(公告)号：US5740065A

公开(公告)日：1998-04-14

申请号：US449853

申请日：1995-05-24

申请人： Young-Chul Jang ,  Hyo-Seok Choi ,  Dong-Heui Jang ,  Sun-Yong Lee

发明人： Young-Chul Jang ,  Hyo-Seok Choi ,  Dong-Heui Jang ,  Sun-Yong Lee

IPC分类号： H01L21/02 ,  G03F7/20 ,  G03F9/00 ,  H01L21/68 ,  G01B11/26 ,  G06F17/18

CPC分类号： G03F7/70633 ,  G03F9/7046

摘要： A method for manufacturing a semiconductor device comprises the steps of extracting an optimal working condition by accumulatively averaging accumulated working conditions of lots previously performed in an expectation process to be currently performed in the manufacturing equipment, extracting a correction condition by extracting information for an alignment state of a lower layer performed by the expectation process, and setting the working condition by adding the correction condition to the optimal working condition.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：通过对在制造设备中当前执行的预期处理中先前执行的批量的累积工作条件累积平均来提取最佳工作条件，通过提取校准状态的信息来提取校正条件 通过预期处理执行的下层，并且通过将校正条件添加到最佳工作条件来设定工作条件。

公开(公告)号：US07759203B2

公开(公告)日：2010-07-20

申请号：US12423404

申请日：2009-04-14

申请人： Young-Chul Jang

发明人： Young-Chul Jang

IPC分类号： H01L21/336

CPC分类号： H01L29/7851 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/66818 ,  H01L29/7854

摘要： A MOS transistor that has a protruding portion with a favorable vertical profile and a protruded-shape channel that requires no additional photolithography process, and a method of fabricating the same are provided. A first mask that defines an isolation region of a substrate is overall etched to form a second mask with a smaller width than the first mask. Then, the substrate is etched to a predetermined depth while using the second mask as an etch mask, thereby forming the protruding portion. Without performing a photolithography process, the protruding portion has a favorable profile and the protruding height of an isolation layer is adjusted to be capable of appropriately performing ion implantation upon the protruding portion.

摘要翻译： 具有具有良好垂直剖面的突出部分和不需要附加光刻工艺的突出形状的沟道的MOS晶体管及其制造方法。 限定衬底的隔离区域的第一掩模被总体蚀刻以形成具有比第一掩模更小的宽度的第二掩模。 然后，在使用第二掩模作为蚀刻掩模的同时将基板蚀刻到预定深度，从而形成突出部分。 在不进行光刻处理的情况下，突出部具有良好的轮廓，并且隔离层的突出高度被调整为能够适当地进行离子注入在突出部上。

公开(公告)号：US06211094B1

公开(公告)日：2001-04-03

申请号：US09379565

申请日：1999-08-23

申请人： Kyoung-Shik Jun ,  Young-Chul Jang ,  Bong-Su Cho

发明人： Kyoung-Shik Jun ,  Young-Chul Jang ,  Bong-Su Cho

IPC分类号： H01L2166

CPC分类号： H01L22/26 ,  H01L22/12

摘要： A method of controlling thicknesses of thin film layers in manufacturing semiconductor devices begins with loading monitoring wafers in a thin film forming apparatus. The apparatus has multiple film formation zones, and one of the zones is a reference zone. After forming thin films on the monitoring wafers, thicknesses of the thin films formed on the monitoring wafers are measured. Then, process time and process temperatures are adjusted so that the thicknesses of films are the same as a target film thickness. Finally, thin films are formed on semiconductor wafers using the adjusted process time and temperatures.

摘要翻译： 在制造半导体器件中控制薄膜层的厚度的方法首先将监测晶片装载在薄膜形成装置中。 该装置具有多个成膜区，其中一个区是参考区。 在监视晶片上形成薄膜之后，测量在监视晶片上形成的薄膜的厚度。 然后，调整处理时间和处理温度，使得膜的厚度与目标膜厚度相同。 最后，使用经调整的处理时间和温度在半导体晶片上形成薄膜。

公开(公告)号：US5863807A

公开(公告)日：1999-01-26

申请号：US616896

申请日：1996-03-15

申请人： Young-Chul Jang ,  Bo-Yeon Shim ,  Chung-Sam Ahn

发明人： Young-Chul Jang ,  Bo-Yeon Shim ,  Chung-Sam Ahn

IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/66

CPC分类号： H01L22/20

摘要： A method of manufacturing a semiconductor device having a plurality of measuring steps performed by a plurality of measuring equipment comprising the steps of; (a) determining the operational state of each one of the plurality of measuring equipment, (b) selecting and performing a measuring step from the plurality of measuring steps in accordance with the determination made in step (a), and repeating steps (a) and (b) until the plurality of measuring steps is completed.

摘要翻译： 一种制造具有由多个测量设备执行的多个测量步骤的半导体器件的方法，包括以下步骤： （a）确定多个测量设备中的每个测量设备的操作状态，（b）根据步骤（a）中确定的多个测量步骤选择和执行测量步骤，并重复步骤（a） 和（b）直到多个测量步骤完成。