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21.发明授权
公开(公告)号：US4823363A
公开(公告)日：1989-04-18
申请号：US882163
申请日：1986-07-07
申请人： Yasuharu Yoshida
发明人： Yasuharu Yoshida
摘要： In a digital transmission system, a clock regeneration circuit includes a phase-locked loop having a low-pass filter, a voltage-controlled oscillator connected thereto, and a phase comparator for supplying to the low-pass filter a signal representative of the phase difference between an incoming two-level data bit stream and the output of the voltage-controlled oscillator. The incoming data bit stream is converted into a plurality of parallel data bit streams and fed to a multi-level quadrature amplitude modulator in response to a clock signal derived from the output of the voltage-controlled oscillator and converted into an outgoing multi-level digital signal. An incoming CMI (coded mark inversion) coded binary signal is sampled by a flip-flop for in response to the output of the voltage-controlled oscillator to supply an output signal to the VCO through the low-pass filter.
摘要翻译： 在数字传输系统中，时钟再生电路包括具有低通滤波器的锁相环，与其连接的压控振荡器和用于向低通滤波器提供表示相位差的信号的相位比较器 在输入的两电平数据位流与压控振荡器的输出之间。 输入数据比特流被转换成多个并行数据比特流，并响应于从压控振荡器的输出导出的时钟信号并馈送到多电平正交幅度调制器，并被转换成输出多电平数字 信号。 通过触发器对进入的CMI（编码标记反转）编码的二进制信号进行采样，以响应压控振荡器的输出，通过低通滤波器向VCO提供输出信号。
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公开(公告)号：US4755763A
公开(公告)日：1988-07-05
申请号：US882326
申请日：1986-07-07
申请人： Yasuharu Yoshida
发明人： Yasuharu Yoshida
CPC分类号： H04L27/3818
摘要： In a demodulator for use in demodulating a quadrature amplitude modulated signal into a first and a second digital signal by the use of a reproduction of a carrier wave, a pull-in phase is detected by a pull-in phase discriminator (55) after establishment of synchronization. The reproduction of the carrier wave is momentarily phase shifted in a phase modulator (65, 65') with reference to the pull-in phase and is produced as a phase shifted carrier signal. The resultant pull-in phase is momentarily corrected to avoid abnormal demodulation. Detection of the pull-in phase is possible either by monitoring a demodulating analog signal and the first and the second digital signals or by monitoring only the first and the second digital signals. The phase modulator may be either a two-phase modulator or a n.pi./2-phase one where n is a natural number between unity and three, both inclusive.
摘要翻译： 在用于通过使用载波的再现将正交幅度调制信号解调为第一和第二数字信号的解调器中，在建立之后由引入相位鉴别器（55）检测引入相位 的同步。 参考引入相位，相位调制器（65,65'）中的载波的再现暂时相移，并被产生为相移载波信号。 所产生的拉入相被短暂校正以避免异常解调。 可以通过监视解调模拟信号和第一和第二数字信号或仅监视第一和第二数字信号来检测拉入相位。 相位调制器可以是两相调制器或n pi / 2相，其中n是在一个和三个之间的自然数，包括两端。
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23.发明授权D/A converter capable of producing an analog signal having levels of a preselected number different from 2.sup.N and communication network comprising the D/A converter 失效D / A转换器，其能够产生具有不同于2N的预选数量的模拟信号和包括D / A转换器的通信网络
公开(公告)号：US4750191A
公开(公告)日：1988-06-07
申请号：US794662
申请日：1985-11-04
申请人： Yasuharu Yoshida
发明人： Yasuharu Yoshida
CPC分类号： H04L27/3411 , H03M1/664
摘要： In a digital-to-analog converter, a digital input signal of x bits is subjected to digital-to-analog conversion with at least two of x bit positions recognized as a common bit position and converted into analog levels of a number which is different from 2.sup.x where x is an integer. At least one additional common bit position may be selected from the x bit positions except the common bit position. The digital input signal may be pre-processed by the use of a logic circuit prior to the digital-to-analog conversion so as to control the number of analog levels. The digital-to-analog converter is applicable to a modulator which produces a quadrature amplitude modulated signal having a circular arrangement of signal points on a phase plane. A demodulator comprises an analog-to-digital converter for converting the above-mentioned analog signal into a reproduction of the digital input signal.
摘要翻译： 在数模转换器中，x位的数字输入信号经受数字到模拟转换，其中至少两个x位位置被识别为公共位位置，并被转换为不同的数字的模拟电平 从2x，其中x是整数。 可以从除了公共位位置之外的x位位置中选择至少一个附加的公共位位置。 数字输入信号可以在数模转换之前通过使用逻辑电路进行预处理，以便控制模拟电平的数量。 数模转换器适用于产生在相位平面上具有信号点圆形布置的正交幅度调制信号的调制器。 解调器包括用于将上述模拟信号转换为数字输入信号的再现的模拟 - 数字转换器。
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24.发明授权Demodulator with AGC circuit for multi-level quadrature amplitude-modulated carrier wave 失效具有AGC电路的解调器用于多电平正交调幅载波
公开(公告)号：US4574246A
公开(公告)日：1986-03-04
申请号：US589265
申请日：1984-03-13
申请人： Yasuharu Yoshida
发明人： Yasuharu Yoshida
CPC分类号： H04L27/3809
摘要： A demodulator for a multi-level quadrature amplitude-modulated carrier wave includes an AGC amplifier receiving the multi-level quadrature amplitude-modulated wave, the amplifier output being coupled to a quadrature phase demodulator producing an inphase and quadrature-phase demodulated signal. An automatic gain control amplifier receives an output of the quadrature-phase demodulator to compensate for the gain difference between the inphase and quadrature-phase signals. The gain difference compensated inphase and quadrature-phase signals are applied to first and second multi-level discriminators.
摘要翻译： 用于多电平正交幅度调制载波的解调器包括接收多电平正交幅度调制波的AGC放大器，放大器输出耦合到产生同相和正交相位解调信号的正交相位解调器。 自动增益控制放大器接收正交相位解调器的输出，以补偿同相和正交相位信号之间的增益差。 增益差补偿同相和正交相位信号被施加到第一和第二多电平鉴别器。
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公开(公告)号：US4498050A
公开(公告)日：1985-02-05
申请号：US491487
申请日：1983-05-04
申请人： Yasuharu Yoshida
发明人： Yasuharu Yoshida
摘要： A demodulator for a composite PSK-PSK modulated signal having a 2.sup.n -phase main data signal and a 2-phase subdata signal including a frame signal, said demodulator comprising an orthogonal detector 21 producing two orthogonally demodulated signals P, Q, a subdata reproducing section 50 for phase-shifting the orthogonal signals and multiplying together the phase-shifted signals to reproduce the subdata signal, a lock-in phase discriminator 42 for detecting the frame synchronization, and a main data reproducing section 51 for phase-shifting and switching the orthogonal signals in response to the phase discriminator and the reproduced subdata signal to reproduce the main signal.
摘要翻译： 一种用于具有2n相主数据信号和包括帧信号的2相子数据信号的复合PSK-PSK调制信号的解调器，所述解调器包括产生两个正交解调信号P，Q的正交检测器21，子数据再现部分 50，用于对正交信号进行相位偏移并将相移信号相乘以再现子数据信号;锁定相位鉴别器42，用于检测帧同步;以及主数据再现部分51，用于对正交信号进行相移和切换 响应于相位鉴别器和再现的子数据信号的信号再现主信号。
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26.发明授权
公开(公告)号：US4095187A
公开(公告)日：1978-06-13
申请号：US779853
申请日：1977-03-21
申请人： Yasuharu Yoshida
发明人： Yasuharu Yoshida
IPC分类号： H03D3/24 , H04L27/227 , H04L27/38 , H03D3/20
CPC分类号： H04L27/2277 , H03D3/241 , H04L27/2272 , H04L27/2275 , H04L27/38
摘要： A demodulation system for demodulating a multi-level, multi-phase, superposition-modulated carrier wave is disclosed. The demodulation system includes a phase-detecting circuit and first and second demodulator circuits. The first demodulator circuit discriminates the output of the phase-detecting circuit to reproduce a first demodulated signal. The second demodulator circuit squares the output of the phase-detecting circuit and discriminates the squared output with respect to a given level. The resulting signal is then combined with the output of the first demodulator circuit in Exclusive-OR logic to obtain a second demodulated signal.
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公开(公告)号：US07464133B1
公开(公告)日：2008-12-09
申请号：US10048999
申请日：1999-10-05
申请人： Takami Kasasaku , Yasuharu Yoshida
发明人： Takami Kasasaku , Yasuharu Yoshida
IPC分类号： G06F15/16
摘要： The server/client system comprises a server and at least one client which is connected to said server via a communication line and is provided with at least one I/O port, and is so configured that said server is provided with a device driver for controlling said I/O port, and a virtual I/O port for providing an interface having the same function as said I/O port for said device driver, for transmitting an input/output control signal from said device driver to said client, and for receiving an event from said client to indicate said event to said device driver, and said client is provided with a device handler which is connected to said virtual I/O port via said communication line and controls said I/O port.
摘要翻译： 服务器/客户端系统包括服务器和经由通信线路连接到所述服务器的至少一个客户端，并且设置有至少一个I / O端口，并且被配置为使得所述服务器设置有用于控制的设备驱动器 所述I / O端口和用于提供与所述设备驱动器的所述I / O端口具有相同功能的接口的虚拟I / O端口，用于将来自所述设备驱动程序的输入/输出控制信号发送到所述客户端，并且 从所述客户端接收到向所述设备驱动程序指示所述事件的事件，并且所述客户机被提供有经由所述通信线路连接到所述虚拟I / O端口并控制所述I / O端口的设备处理器。
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公开(公告)号：US07099625B1
公开(公告)日：2006-08-29
申请号：US09348169
申请日：1999-07-07
申请人： Yasuharu Yoshida
发明人： Yasuharu Yoshida
IPC分类号： H04B15/00
摘要： An automobile communication system which can ensure fast hand-over without putting unnecessary burden on mobile stations and can adequately handle changes in road condition is disclosed. For each of the radio zones formed by roadside transceivers arranged along a road, a plurality of transmission and reception frequencies ft1/fr1 and ft2/fr2 are provided. The in-use transmission/reception frequencies in adjoining radio zones are switched at predetermined timing such that they are not permitted to be overlapped. By switching a time slot allocated to the vehicle-mounted transceiver, the vehicle-mounted transceiver can continuously communicate with the roadside transceivers at the same communication frequency over the radio zones.
摘要翻译： 一种汽车通信系统，可以确保快速切换，而不会对移动台造成不必要的负担，并且可以适当地处理路况的变化。 对于沿着沿道路布置的路边收发器形成的每个无线电区域，多个发送和接收频率f 1，t 2，f 2，t 2， > / f 。 在相邻的无线电区域中的使用中的发送/接收频率在预定的定时被切换，使得它们不被重叠。 通过切换分配给车载收发器的时隙，车载收发器可以通过无线电区域以相同的通信频率与路边收发器连续通信。
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公开(公告)号：US4799240A
公开(公告)日：1989-01-17
申请号：US863771
申请日：1986-05-15
申请人： Yasuharu Yoshida
发明人： Yasuharu Yoshida
CPC分类号： H04L7/027
摘要： A clock synchronizing circuit separates and filters a clock component from a digital input wave. The output of the circuit is sampled to produce a two-level signal. A voltage controlled oscillator generates a clock signal having a phase and a frequency which is controlled responsive to the two-level signal.
摘要翻译： 时钟同步电路从数字输入波分离和滤波时钟分量。 对电路的输出进行采样以产生两级信号。 压控振荡器产生具有响应于两电平信号被控制的相位和频率的时钟信号。
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30.发明授权Multilevel modulator capable of producing a composite modulated signal comprising a quadrature amplitude modulated component and a phase modulated component 失效能够产生包括正交幅度调制分量和相位调制分量的复合调制信号的多电平调制器
公开(公告)号：US4751478A
公开(公告)日：1988-06-14
申请号：US12405
申请日：1987-02-09
申请人： Yasuharu Yoshida
发明人： Yasuharu Yoshida
CPC分类号： H04L27/363 , H04L27/3461 , H04L27/3827
摘要： Responsive to a first and a second main data signal and a subdata signal, a multilevel modulator produces a composite modulated signal which comprises a quadrature amplitude modulated component modulated by the first and the second main data signals and represented by a radius on a phase plane and a phase modulated component modulated by the subdata signal are represented by a clockwise and a counterclockwise shift on the phase plane. A multilevel demodulator carries out an inverse operation to reproduce the composite modulated signal into first and second reproduced main data signal and a reproduced subdata signal.
摘要翻译： 响应于第一和第二主数据信号和子数据信号，多电平调制器产生复合调制信号，该复合调制信号包括由第一和第二主数据信号调制并由相平面上的半径表示的正交幅度调制分量， 由子数据信号调制的相位调制分量由相位平面上的顺时针和逆时针偏移表示。 多电平解调器执行逆运算以将复合调制信号再现成第一和第二再现主数据信号和再现的子数据信号。
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