公开(公告)号：US20130204549A1

公开(公告)日：2013-08-08

申请号：US13574477

申请日：2011-05-18

申请人： Masanobu Saito ,  Keisuke Kodera ,  Masatoyo Oshiro

发明人： Masanobu Saito ,  Keisuke Kodera ,  Masatoyo Oshiro

IPC分类号： G01N7/14

CPC分类号： G01N7/14 ,  A61L2/208 ,  A61L2202/14

摘要： It is determined that indoor condensation of hydrogen peroxide vapor is to occur, if there is a solution with which both (Equation 1): PT·y1=P01·x1·γ1 and (Equation 2): PT·y2=P02·x2·γ2 hold. With this, it is possible to accurately determine whether indoor condensation of hydrogen peroxide vapor is to occur or not in decontamination.

摘要翻译： 如果存在两个（等式1）：PT·y1 = P01·x1·γ1和（等式2）的解决方案，则确定过氧化氢蒸气的室内冷凝：PT·y2 = P02·x2· 伽马2持有。 由此，能够精确地确定在去污中是否发生过氧化氢蒸气的室内冷凝。

公开(公告)号：US07612401B2

公开(公告)日：2009-11-03

申请号：US11338654

申请日：2006-01-25

申请人： Yoshio Ozawa ,  Shigehiko Saida ,  Yuji Takeuchi ,  Masanobu Saito

发明人： Yoshio Ozawa ,  Shigehiko Saida ,  Yuji Takeuchi ,  Masanobu Saito

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

摘要翻译： 半导体器件包括半导体衬底和设置在半导体衬底上的非易失性存储单元，所述非易失性存储单元包括隧道绝缘膜，所述隧道绝缘膜具有在非易失性的沟道宽度方向周期性且连续变化的膜厚度 存储单元，设置在隧道绝缘膜上的浮置栅电极，设置在浮置栅电极上方的控制栅电极，以及设置在控制栅电极和浮栅之间的电极间绝缘膜。

公开(公告)号：US07426482B2

公开(公告)日：2008-09-16

申请号：US10225244

申请日：2002-08-22

申请人： Satoru Inami ,  Masanobu Saito ,  Seiichi Shinohara ,  Takayuki Namiki

发明人： Satoru Inami ,  Masanobu Saito ,  Seiichi Shinohara ,  Takayuki Namiki

IPC分类号： G06Q15/10

CPC分类号： G06Q10/087 ,  G06Q30/02 ,  G06Q30/0637

摘要： In an image processing apparatus that includes an order placement means for executing an operation associated with order placement of an expendable used in an image forming apparatus, data associated with image formation is accumulated to have a timing associated with order placement as a trigger, and the operation of the order placement means is controlled on the basis of the accumulated value. In this manner, redundant orders for expendables can be prevented.

摘要翻译： 在包括用于执行与在图像形成装置中使用的消耗品的订单放置相关联的操作的订单放置装置的图像处理装置中，与图像形成相关联的数据被累积以具有与订单布置相关联的定时作为触发，并且 基于累计值来控制订单放置装置的操作。 以这种方式，可以防止消耗品的冗余订单。

公开(公告)号：US20050224898A1

公开(公告)日：2005-10-13

申请号：US11143594

申请日：2005-06-03

申请人： Hisayo Momose ,  Hiroshi Iwai ,  Masanobu Saito ,  Tatsuya Ohguro ,  Mizuki Ono ,  Takashi Yoshitomi ,  Shinichi Nakamura

发明人： Hisayo Momose ,  Hiroshi Iwai ,  Masanobu Saito ,  Tatsuya Ohguro ,  Mizuki Ono ,  Takashi Yoshitomi ,  Shinichi Nakamura

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/28211 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/78

摘要： A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed an the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 μm; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined a be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.

摘要翻译： 半导体器件包括：p型半导体衬底（1）; 绝缘膜（3）; 经由所述绝缘膜形成所述基板的栅电极（2） 以及形成在形成在基板（1）上的栅电极（2）下方的沟道形成区域（4）的两侧的n型源极/漏极区域（5）。 特别地，在氧化硅膜的转换率（氧化硅当量厚度）下，确定绝缘膜（3）的厚度（T×OX ）小于2.5nm。 栅极（2）的栅极长度（L SUB）确定为等于或小于0.3μm; 并且进一步施加到栅电极（2）和漏区（6）的电压为1.5V以下。 因此，在具有隧穿栅极氧化膜（3）的MOSFET中，可以提高热载流子应力下的晶体管的可靠性，并且可以显着降低栅极漏电流，从而可以显着提高晶体管特性。

公开(公告)号：US06954596B2

公开(公告)日：2005-10-11

申请号：US10649835

申请日：2003-08-28

申请人： Masanobu Saito ,  Marehiko Hirajima

发明人： Masanobu Saito ,  Marehiko Hirajima

IPC分类号： G03G21/00 ,  G03G15/16 ,  G03G21/18 ,  G03G15/00

CPC分类号： G03G21/1889

摘要： An image forming apparatus in which information regarding used amounts in image forming apparatus main bodies of different features is stored in the storage part of a cartridge, and the interchange time of the cartridge is judged by the use of the information. Thereby, even if a cartridge having interchangeability between a plurality of kinds of image forming apparatus main bodies of different features is mounted on each of the main bodies of different features, an interchange time corresponding to the main body can be grasped accurately.

摘要翻译： 一种图像形成装置，其中关于在不同特征的图像形成装置主体中的使用量的信息存储在盒的存储部分中，并且通过使用该信息来判断盒的交换时间。 因此，即使在具有不同特征的多种图像形成装置主体之间具有可互换性的盒安装在不同特征的每个主体上，可以准确地掌握对应于主体的交换时间。

公开(公告)号：US06873350B2

公开(公告)日：2005-03-29

申请号：US09887119

申请日：2001-06-25

申请人： Masanobu Saito ,  Satoru Inami ,  Seiichi Shinohara ,  Takayuki Namiki

发明人： Masanobu Saito ,  Satoru Inami ,  Seiichi Shinohara ,  Takayuki Namiki

IPC分类号： B41J2/44 ,  G02B26/10 ,  G06K15/12 ,  H04N1/113 ,  H04N1/23 ,  B41J2/435

CPC分类号： G06K15/1219

摘要： There is provided an image forming apparatus such as a latent image forming apparatus, in which the density of a half tone is stable independent on a write position of a main scanning line, even if a plurality of semiconductor lasers are used. The image forming apparatus has a latent image forming unit for pulse-width-modulating a drive signal of the semiconductor laser in response to the write position of image data. The latent image forming unit has an image sorting circuit for sorting the image data into an odd line and an even line, a memory for storing a turning on position, a pulse generating position control circuit for generating a pulse generating position signal, a PWM circuit for generating a triangular wave in accordance with the pulse generating position signal, and a beam-A-circuit and a beam-B-circuit, which control beams from the semiconductor laser.

摘要翻译： 提供了一种诸如潜像形成装置的图像形成装置，其中半色调的浓度独立于主扫描线的写入位置是稳定的，即使使用多个半导体激光器。 图像形成装置具有潜像形成单元，用于响应于图像数据的写入位置对半导体激光器的驱动信号进行脉宽调制。 潜像形成单元具有用于将图像数据分类为奇数行和偶数行的图像分类电路，用于存储接通位置的存储器，用于产生脉冲产生位置信号的脉冲产生位置控制电路，PWM电路 用于根据脉冲产生位置信号产生三角波，以及控制来自半导体激光器的光束的光束A电路和光束B电路。

公开(公告)号：US06434054B1

公开(公告)日：2002-08-13

申请号：US10040383

申请日：2002-01-09

申请人： Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

发明人： Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

IPC分类号： G11C1616

CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C2216/20

摘要： A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasion of data from the selected memory. The write state machine executes writing, under a first writing condition, on a predetermined number of memory cells included in the memory cell array, and executes writing on memory cells other than the predetermined number of memory cells, under a second writing condition set in accordance with a result of the writing executed under the first writing condition.

摘要翻译： 根据本发明的非易失性半导体存储器件包括具有多个非易失性存储单元的存储单元阵列，以及控制施加到从存储单元阵列选择的存储单元的电压的写状态机和施加电压的周期 根据从所选择的存储器单元读取数据的每一个，将数据写入所选存储单元，以及从所选存储器中擦除数据。 写入状态机在第一写入条件下执行包含在存储单元阵列中的预定数量的存储单元上的写入，并且在按照相应设置的第二写入条件下执行对除了预定数量的存储单元之外的存储单元的写入 其结果是在第一写入条件下执行写入。

公开(公告)号：US06351417B1

公开(公告)日：2002-02-26

申请号：US09833687

申请日：2001-04-13

申请人： Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

发明人： Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

IPC分类号： G11C1616

CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C2216/20

摘要： A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasing of data from the selected memory. The write state machine executes writing, under a first writing condition, on a predetermined number of memory cells included in the memory cell array, and executes writing on memory cells other than the predetermined number of memory cells, under a second writing condition set in accordance with a result of the writing executed under the first writing condition.

摘要翻译： 根据本发明的非易失性半导体存储器件包括具有多个非易失性存储单元的存储单元阵列，以及控制施加到从存储单元阵列选择的存储单元的电压的写状态机和施加电压的周期 根据从所选存储单元读取数据的每一个，将数据写入所选存储单元，以及从所选存储器擦除数据。 写入状态机在第一写入条件下执行包含在存储单元阵列中的预定数量的存储单元上的写入，并且在按照相应设置的第二写入条件下执行对除了预定数量的存储单元之外的存储单元的写入 其结果是在第一写入条件下执行写入。

公开(公告)号：US06217879B1

公开(公告)日：2001-04-17

申请号：US09397014

申请日：1999-09-15

申请人： Kunio Suetsuna ,  Masanobu Saito

发明人： Kunio Suetsuna ,  Masanobu Saito

IPC分类号： A61K3578

CPC分类号： A61K36/04 ,  A23L33/18 ,  A23V2002/00 ,  A23V2250/202

摘要： The present invention provides materials from laver (a seaweed) as the starting material, which are useful in the field of pharmaceutical preparation, the field of health food, etc. The present invention relates to enzyme-decomposed materials from laver comprising a peptide mixture having an antihypertensive action obtained by decomposing laver with pepsin, wherein laver is boiled as a starting material for 1 hour or more and then the broth is removed whereby their antihypertensive action is further raised while their bitter taste, smell, viscosity etc. are eliminated. Accordingly, these enzyme-decomposed materials are made further useful as an antihypertensive agent and also suitable when added to food for use as health food. Further, these materials after decomposed with pepsin are further decomposed with an enzyme having a peptidase activity thereby improving tastes and providing more suitable food additives.

摘要翻译： 本发明提供了可用于药物制剂领域的紫菜（海藻）作为起始原料的材料，保健食品领域等。本发明涉及来自紫菜的酶分解物质，其包含具有 通过用胃蛋白酶分解紫菜获得的抗高血压作用，其中将紫菜作为起始原料煮沸1小时以上，然后除去肉汤，从而进一步升高其降压作用，同时消除其苦味，气味，粘度等。 因此，这些酶分解材料作为抗高血压剂进一步有用，并且当添加到用作保健食品的食品中时也是合适的。 此外，用胃蛋白酶分解后的这些物质进一步用具有肽酶活性的酶分解，从而改善口味并提供更合适的食品添加剂。

公开(公告)号：US5698881A

公开(公告)日：1997-12-16

申请号：US353240

申请日：1994-12-02

申请人： Takashi Yoshitomi ,  Masanobu Saito ,  Hisayo Momose ,  Hiroshi Iwai ,  Yukihiro Ushiku ,  Mizuki Ono ,  Yasushi Akasaka ,  Hideaki Nii ,  Satoshi Matsuda ,  Yasuhiro Katsumata ,  Tatsuya Ooguro ,  Claudio Fiegna

发明人： Takashi Yoshitomi ,  Masanobu Saito ,  Hisayo Momose ,  Hiroshi Iwai ,  Yukihiro Ushiku ,  Mizuki Ono ,  Yasushi Akasaka ,  Hideaki Nii ,  Satoshi Matsuda ,  Yasuhiro Katsumata ,  Tatsuya Ooguro ,  Claudio Fiegna

IPC分类号： H01L21/033 ,  H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/0338 ,  H01L21/2255 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66628

摘要： A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j �nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff �nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.

摘要翻译： MOS型半导体器件具有长度为170nm（0.17μm）以下的栅极，沟道附近的源极和漏极扩散层的结深度为22nm以下，表面上的杂质浓度 在源极和漏极扩散层中形成1020cm-3以上。 这种结构使用从950℃到1050℃的热范围的固相扩散和/或通过灰化或蚀刻使栅极宽度变窄来获得。 其他MOS型半导体器件的特征在于源极和漏极扩散层区域中的结深度xj [nm]与有效沟道长度Leff [nm]之间的关系由Leff> 0.69×j-6.17确定。