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    High Density MOSFET Array with Self-Aligned Contacts Delimited by Nitride-Capped Trench Gate Stacks and Method
    21.
    发明申请
    High Density MOSFET Array with Self-Aligned Contacts Delimited by Nitride-Capped Trench Gate Stacks and Method 有权
    高密度MOSFET阵列，具有由氮化物覆盖的沟槽栅极分隔的自对准触点和方法

    公开(公告)号：US20140252460A1

    公开(公告)日：2014-09-11

    申请号：US13794628

    申请日：2013-03-11

    申请人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

    发明人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L27/088 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.

    摘要翻译： 公开了一种高密度沟槽门控MOSFET阵列和方法。 它包括分为MOSFET阵列区域和栅极拾取区域的半导体衬底; 外延区域，体区域和源区域; 许多精确间隔的活性氮化物封闭沟槽栅堆叠（ANCTGS）嵌入到外延区域。 每个ANCTGS包括堆叠的多晶硅沟槽栅极，栅极氧化物层和覆盖多晶硅沟槽栅极顶部的氮化硅盖，并横向配向栅极氧化物壳。 ANCTGS与MOSFET阵列区域中的源极，主体，外延区域，MOSFET器件一起形成。 在MOSFET阵列区域和栅极拾取区域上，MOSFET阵列顶部的图案化电介质区域和图案化电介质区域顶部的图案化金属层。 因此，图案化的金属层与MOSFET阵列和栅极拾取区域形成自对准的源极和主体通过ANCTGS间隔而接触。

    Manufacturing methods for accurately aligned and self-balanced superjunction devices
    22.
    发明授权
    Manufacturing methods for accurately aligned and self-balanced superjunction devices 有权
    精确对准和自平衡超级结装置的制造方法

    公开(公告)号：US08785306B2

    公开(公告)日：2014-07-22

    申请号：US13200683

    申请日：2011-09-27

    申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

    发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

    IPC分类号： H01L29/06

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

    摘要： A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

    摘要翻译： 一种在半导体基板上制造半导体功率器件的方法，该半导体衬底通过生长第一外延层，然后在外延层的顶部上形成第一硬掩模层，从而支撑由外延层组成的漂移区; 施加第一注入掩模以打开多个植入窗口并且施加第二注入掩模以阻挡所述植入物窗口中的一些以在所述第一外延层中相互邻近地注入交替导电类型的多个掺杂区域; 通过施加相同的第一和第二注入掩模来重复第一步骤和第二步骤，以形成多个外延层，然后利用扩散处理在外延层的顶侧上进行器件制造工艺，以将掺杂区域 交替导电类型作为外延层中的掺杂列。

    Method for making a charge balanced multi-nano shell drift region for superjunction semiconductor device
    25.
    发明授权
    Method for making a charge balanced multi-nano shell drift region for superjunction semiconductor device 有权
    用于超级结半导体器件的电荷平衡多纳米壳漂移区域的方法

    公开(公告)号：US07892924B1

    公开(公告)日：2011-02-22

    申请号：US12629793

    申请日：2009-12-02

    申请人： Yeeheng Lee ,  Moses Ho ,  Lingpeng Guan

    发明人： Yeeheng Lee ,  Moses Ho ,  Lingpeng Guan

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/66712

    摘要： A method is disclosed for making a substantially charge balanced multi-nano shell drift region (MNSDR) for superjunction semiconductor devices atop a base substrate. The MNSDR has numerous concentric nano shell members NSM1, NSM2, . . . , NSMM (M>1) of alternating, substantially charge balanced first conductivity type and second conductivity type and with height NSHT. First, a bulk drift layer (BDL) is formed atop the base substrate. A substantially vertical cavity of pre-determined shape and size and with depth NSHT is then created into the top surface of BDL. The shell members NSM1, NSM2, . . . , NSMM are successively formed inside the vertical cavity, initially upon its vertical walls then moving toward its center, so as to successively fill the vertical cavity till a residual space remains therein. A semi-insulating or insulating fill-up nano plate is then formed inside the residual space to fill it up.

    摘要翻译： 公开了一种用于在基底基板顶上形成用于超结半导体器件的基本电荷平衡的多纳米壳漂移区（MNSDR）的方法。 MNSDR有许多同心纳米壳成员NSM1，NSM2。 。 。 ，NSMM（M> 1）交替，基本上电荷平衡的第一导电类型和第二导电类型和高度NSHT。 首先，在基底上形成体漂移层（BDL）。 然后在BDL的顶表面中形成具有预定形状和尺寸并且具有深度NSHT的基本垂直的腔。 外壳成员NSM1，NSM2，。 。 。 NSMM连续地形成在垂直腔内，最初在其垂直壁上然后向其中心移动，以便连续地填充垂直空腔，直到剩余空间保持在其中。 然后在剩余空间内形成半绝缘或绝缘填充纳米板以填充其。

    HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES
    26.
    发明申请
    HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES 有权
    高密度TRENCH MOSFET，具有单面罩预定门和接触孔

    公开(公告)号：US20100190307A1

    公开(公告)日：2010-07-29

    申请号：US12362414

    申请日：2009-01-29

    申请人： Yeeheng Lee ,  Hong Chang ,  Tiesheng Li ,  John Chen ,  Anup Bhalla

    发明人： Yeeheng Lee ,  Hong Chang ,  Tiesheng Li ,  John Chen ,  Anup Bhalla

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/78

    摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

    摘要翻译： 沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。 在半导体基板的表面上形成硬掩模。 在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。 这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。 接下来将栅极沟槽掩模施加在硬掩模的顶部上。 栅极沟槽掩模覆盖主体接触沟槽，并且在栅极沟槽处具有比那些沟槽更宽的开口。 栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。 第一种导电材料可以填充栅沟以形成栅极。 第二种导电材料可以填充身体接触沟槽以形成身体接触。

    High density MOSFET array with self-aligned contacts delimited by nitride-capped trench gate stacks and method
    28.
    发明授权
    High density MOSFET array with self-aligned contacts delimited by nitride-capped trench gate stacks and method 有权
    具有由氮化物封闭的沟槽栅极叠层限定的自对准触点的高密度MOSFET阵列和方法

    公开(公告)号：US09136377B2

    公开(公告)日：2015-09-15

    申请号：US13794628

    申请日：2013-03-11

    申请人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

    发明人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L27/088 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.

    摘要翻译： 公开了一种高密度沟槽门控MOSFET阵列和方法。 它包括分为MOSFET阵列区域和栅极拾取区域的半导体衬底; 外延区域，体区域和源区域; 许多精确间隔的活性氮化物封闭沟槽栅堆叠（ANCTGS）嵌入到外延区域。 每个ANCTGS包括堆叠的多晶硅沟槽栅极，栅极氧化物层和覆盖多晶硅沟槽栅极顶部的氮化硅盖，并横向配向栅极氧化物壳。 ANCTGS与源极，体，外延区域，MOSFET阵列区域中的MOSFET器件一起形成。 在MOSFET阵列区域和栅极拾取区域上，MOSFET阵列顶部的图案化电介质区域和图案化电介质区域顶部的图案化金属层。 因此，图案化的金属层与MOSFET阵列和栅极拾取区域形成自对准的源极和主体通过ANCTGS间隔而接触。

    HIGH DENSITY MOSFET ARRAY WITH SELF-ALIGNED CONTACTS ENHANCEMENT PLUG AND METHOD
    29.
    发明申请
    HIGH DENSITY MOSFET ARRAY WITH SELF-ALIGNED CONTACTS ENHANCEMENT PLUG AND METHOD 有权
    具有自对准接触器的高密度MOSFET阵列增强插头和方法

    公开(公告)号：US20150255565A1

    公开(公告)日：2015-09-10

    申请号：US14197216

    申请日：2014-03-05

    申请人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

    发明人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

    IPC分类号： H01L29/51 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423

    CPC分类号： H01L29/4236 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7813

    摘要： A semiconductor substrate comprises epitaxial region, body region and source region; an array of interdigitated active nitride-capped trench gate stacks (ANCTGS) and self-guided contact enhancement plugs (SGCEP) disposed above the semiconductor substrate and partially embedded into the source region, the body region and the epitaxial region forming the trench-gated MOSFET array. Each ANCTGS comprises a stack of a polysilicon trench gate embedded in a gate oxide shell and a silicon nitride spacer cap covering the top of the polysilicon trench gate; each SGCEP comprises a lower intimate contact enhancement section (ICES) in accurate registration to its neighboring ANCTGS; an upper distal contact enhancement section (DCES) having a lateral mis-registration (LTMSRG) to the neighboring ANCTGS; and an intervening tapered transitional section (TTS) bridging the ICES and the DCES; a patterned metal layer atop the patterned dielectric region atop the MOSFET array forms self-guided source and body contacts through the SGCEP.

    摘要翻译： 半导体衬底包括外延区域，体区域和源极区域; 交错式活性氮化物封闭沟槽栅极叠层阵列（ANCTGS）和自导向接触增强插座（SGCEP），其设置在半导体衬底上并部分地嵌入到源极区域中，体区和形成沟槽栅MOSFET的外延区 数组。 每个ANCTGS包括嵌入在栅极氧化物壳中的多晶硅沟槽栅极的叠层和覆盖多晶硅沟槽栅极的顶部的氮化硅隔离层盖; 每个SGCEP包括一个低密度接触增强部分（ICES），准确地注册到其相邻的ANCTGS; 具有向相邻ANCTGS的横向错配（LTMSRG）的上远端接触增强部分（DCES）; 以及桥接ICES和DCES的中间锥形过渡部分（TTS）; 在MOSFET阵列顶部的图案化电介质区域顶部的图案化金属层通过SGCEP形成自引导源和体接触。