公开(公告)号：US20140252460A1

公开(公告)日：2014-09-11

申请号：US13794628

申请日：2013-03-11

申请人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

发明人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L27/088 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.

摘要翻译： 公开了一种高密度沟槽门控MOSFET阵列和方法。 它包括分为MOSFET阵列区域和栅极拾取区域的半导体衬底; 外延区域，体区域和源区域; 许多精确间隔的活性氮化物封闭沟槽栅堆叠（ANCTGS）嵌入到外延区域。 每个ANCTGS包括堆叠的多晶硅沟槽栅极，栅极氧化物层和覆盖多晶硅沟槽栅极顶部的氮化硅盖，并横向配向栅极氧化物壳。 ANCTGS与MOSFET阵列区域中的源极，主体，外延区域，MOSFET器件一起形成。 在MOSFET阵列区域和栅极拾取区域上，MOSFET阵列顶部的图案化电介质区域和图案化电介质区域顶部的图案化金属层。 因此，图案化的金属层与MOSFET阵列和栅极拾取区域形成自对准的源极和主体通过ANCTGS间隔而接触。

公开(公告)号：US09136377B2

公开(公告)日：2015-09-15

申请号：US13794628

申请日：2013-03-11

申请人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

发明人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L27/088 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.

摘要翻译： 公开了一种高密度沟槽门控MOSFET阵列和方法。 它包括分为MOSFET阵列区域和栅极拾取区域的半导体衬底; 外延区域，体区域和源区域; 许多精确间隔的活性氮化物封闭沟槽栅堆叠（ANCTGS）嵌入到外延区域。 每个ANCTGS包括堆叠的多晶硅沟槽栅极，栅极氧化物层和覆盖多晶硅沟槽栅极顶部的氮化硅盖，并横向配向栅极氧化物壳。 ANCTGS与源极，体，外延区域，MOSFET阵列区域中的MOSFET器件一起形成。 在MOSFET阵列区域和栅极拾取区域上，MOSFET阵列顶部的图案化电介质区域和图案化电介质区域顶部的图案化金属层。 因此，图案化的金属层与MOSFET阵列和栅极拾取区域形成自对准的源极和主体通过ANCTGS间隔而接触。

公开(公告)号：US20150255565A1

公开(公告)日：2015-09-10

申请号：US14197216

申请日：2014-03-05

申请人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

发明人： Yeeheng Lee ,  Jongoh Kim ,  Hong Chang

IPC分类号： H01L29/51 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423

CPC分类号： H01L29/4236 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7813

摘要： A semiconductor substrate comprises epitaxial region, body region and source region; an array of interdigitated active nitride-capped trench gate stacks (ANCTGS) and self-guided contact enhancement plugs (SGCEP) disposed above the semiconductor substrate and partially embedded into the source region, the body region and the epitaxial region forming the trench-gated MOSFET array. Each ANCTGS comprises a stack of a polysilicon trench gate embedded in a gate oxide shell and a silicon nitride spacer cap covering the top of the polysilicon trench gate; each SGCEP comprises a lower intimate contact enhancement section (ICES) in accurate registration to its neighboring ANCTGS; an upper distal contact enhancement section (DCES) having a lateral mis-registration (LTMSRG) to the neighboring ANCTGS; and an intervening tapered transitional section (TTS) bridging the ICES and the DCES; a patterned metal layer atop the patterned dielectric region atop the MOSFET array forms self-guided source and body contacts through the SGCEP.

摘要翻译： 半导体衬底包括外延区域，体区域和源极区域; 交错式活性氮化物封闭沟槽栅极叠层阵列（ANCTGS）和自导向接触增强插座（SGCEP），其设置在半导体衬底上并部分地嵌入到源极区域中，体区和形成沟槽栅MOSFET的外延区 数组。 每个ANCTGS包括嵌入在栅极氧化物壳中的多晶硅沟槽栅极的叠层和覆盖多晶硅沟槽栅极的顶部的氮化硅隔离层盖; 每个SGCEP包括一个低密度接触增强部分（ICES），准确地注册到其相邻的ANCTGS; 具有向相邻ANCTGS的横向错配（LTMSRG）的上远端接触增强部分（DCES）; 以及桥接ICES和DCES的中间锥形过渡部分（TTS）; 在MOSFET阵列顶部的图案化电介质区域顶部的图案化金属层通过SGCEP形成自引导源和体接触。

公开(公告)号：US20140175536A1

公开(公告)日：2014-06-26

申请号：US13724228

申请日：2012-12-21

申请人： Yeeheng Lee ,  Hong Chang ,  Jongoh Kim ,  Sik Liu ,  Hamza Yilmaz ,  Madhur Bobde ,  Daniel Calafut ,  John Chen

发明人： Yeeheng Lee ,  Hong Chang ,  Jongoh Kim ,  Sik Liu ,  Hamza Yilmaz ,  Madhur Bobde ,  Daniel Calafut ,  John Chen

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423 ,  H01L21/033 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/28114 ,  H01L21/3081 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0292 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T2 that is larger than the thickness T1 of an upper portion of the gate oxide. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了具有自对准源触点的高密度基于沟槽的功率MOSFET。 源触点与第一绝缘间隔件和第二绝缘间隔件自对准，其中第一间隔件耐蚀刻工艺，该蚀刻工艺将选择性地去除由第二间隔件制成的材料。 此外，有源器件可以具有两级栅极氧化物，其中栅极氧化物的下部具有大于栅极氧化物的上部的厚度T1的厚度T2。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08803251B2

公开(公告)日：2014-08-12

申请号：US13135982

申请日：2011-07-19

申请人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

发明人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

公开(公告)号：US08785278B2

公开(公告)日：2014-07-22

申请号：US13364948

申请日：2012-02-02

申请人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

发明人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

IPC分类号： H01L21/331

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.

摘要翻译： 半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。 在轻掺杂层中形成一个或多个器件。 每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。 每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。 体区与轻掺杂层和重掺杂层具有相反的导电类型。 源区域靠近上表面形成。 在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。 触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

公开(公告)号：US20130200451A1

公开(公告)日：2013-08-08

申请号：US13364948

申请日：2012-02-02

申请人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

发明人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.

摘要翻译： 半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。 在轻掺杂层中形成一个或多个器件。 每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。 每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。 体区与轻掺杂层和重掺杂层具有相反的导电类型。 源区域靠近上表面形成。 在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。 触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

公开(公告)号：US20160372542A9

公开(公告)日：2016-12-22

申请号：US14329936

申请日：2014-07-12

申请人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

发明人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/761 ,  H01L29/78

CPC分类号： H01L29/0623 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

公开(公告)号：US20160013267A1

公开(公告)日：2016-01-14

申请号：US14329936

申请日：2014-07-12

申请人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

发明人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/761 ,  H01L29/78

CPC分类号： H01L29/0623 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

公开(公告)号：US20100291744A1

公开(公告)日：2010-11-18

申请号：US12847863

申请日：2010-07-30

申请人： Yeeheng Lee ,  Hong Chang ,  Tiesheng Li ,  John Chen ,  Anup Bhalla

发明人： Yeeheng Lee ,  Hong Chang ,  Tiesheng Li ,  John Chen ,  Anup Bhalla

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/78

摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

摘要翻译： 沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。 在半导体基板的表面上形成硬掩模。 在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。 这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。 接下来将栅极沟槽掩模施加在硬掩模的顶部上。 栅极沟槽掩模覆盖主体接触沟槽并且在栅极沟槽处具有开口。 栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。 第一种导电材料可以填充栅沟以形成栅极。 第二种导电材料可以填充身体接触沟槽以形成身体接触。