公开(公告)号：US08357603B2

公开(公告)日：2013-01-22

申请号：US12641560

申请日：2009-12-18

申请人： Bor-Wen Chan ,  Hsueh Wen Tsau ,  Kuang-Yuan Hsu

发明人： Bor-Wen Chan ,  Hsueh Wen Tsau ,  Kuang-Yuan Hsu

IPC分类号： H01L21/4763

CPC分类号： H01L29/7848 ,  H01L21/28079 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7834

摘要： The present disclosure provides various methods of fabricating a semiconductor device. A method of fabricating a semiconductor device includes providing a semiconductor substrate and forming a gate structure over the substrate. The gate structure includes a first spacer and a second spacer formed apart from the first spacer. The gate structure also includes a dummy gate formed between the first and second spacers. The method also includes removing a portion of the dummy gate from the gate structure thereby forming a partial trench. Additionally, the method includes removing a portion of the first spacer and a portion of the second spacer adjacent the partial trench thereby forming a widened portion of the partial trench. In addition, the method includes removing a remaining portion of the dummy gate from the gate structure thereby forming a full trench. A high k film and a metal gate are formed in the full trench.

摘要翻译： 本公开提供制造半导体器件的各种方法。 制造半导体器件的方法包括提供半导体衬底并在衬底上形成栅极结构。 栅极结构包括第一间隔物和与第一间隔物分开形成的第二间隔物。 栅极结构还包括形成在第一和第二间隔物之间​​的虚拟栅极。 该方法还包括从栅极结构中去除伪栅极的一部分，从而形成部分沟槽。 此外，该方法包括移除第一间隔物的一部分和邻近部分沟槽的第二间隔物的一部分，从而形成部分沟槽的加宽部分。 此外，该方法包括从栅极结构中去除伪栅极的剩余部分，从而形成全沟槽。 在整个沟槽中形成高k膜和金属栅极。

公开(公告)号：US08299508B2

公开(公告)日：2012-10-30

申请号：US12757517

申请日：2010-04-09

申请人： Bor Chiuan Hsieh ,  Han-Ping Chung ,  Chih-Hsin Ko ,  Bor-Wen Chan ,  Hun-Jan Tao

发明人： Bor Chiuan Hsieh ,  Han-Ping Chung ,  Chih-Hsin Ko ,  Bor-Wen Chan ,  Hun-Jan Tao

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.

摘要翻译： 半导体器件包括具有浅沟槽隔离和位于其中的源极/漏极区的衬底，位于源极/漏极区之间的衬底上的栅极堆叠，栅极堆叠的侧壁上的第一栅极间隔物和位于栅极堆叠的侧壁上的第二栅极间隔 第一栅极间隔物的侧壁。

公开(公告)号：US07354847B2

公开(公告)日：2008-04-08

申请号：US10764913

申请日：2004-01-26

申请人： Bor-Wen Chan ,  Yi-Chun Huang ,  Baw-Ching Perng ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Yi-Chun Huang ,  Baw-Ching Perng ,  Hun-Jan Tao

IPC分类号： H01L21/3205 ,  H01L27/10

CPC分类号： H01L21/28123 ,  H01L21/0271 ,  H01L21/0338 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823437

摘要： A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2/N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr/O2/Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O2/Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1−w2) is possible than in prior art methods.

摘要翻译： 描述了在MOSFET的栅电极制造期间修整光致抗蚀剂层的工艺。 在较厚的有机底层上具有顶部光致抗蚀剂层的双层叠层以193nm或157nm辐射图案曝光以形成顶层中具有宽度w 1 1的特征。 通过底层的图案转移通过基于H 2 N 2 N 2 N 2 SO 3和SO 2 H 2化学的各向异性蚀刻进行。 通过HBr / O 2 / Cl 2等离子体将形成在双层叠层中的特征修剪10nm以上至宽度w 2 2 <！ - SIPO

公开(公告)号：US20060148181A1

公开(公告)日：2006-07-06

申请号：US11026009

申请日：2004-12-31

申请人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Han-Jan Tao

发明人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Han-Jan Tao

IPC分类号： H01L21/8238

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/938

摘要： A strained channel NMOS and PMOS device pair including fully silicided gate electrodes and method for forming the same, the method including providing a semiconductor substrate including NMOS and PMOS device regions including respective gate structures including polysilicon gate electrodes; forming recessed regions on either side of a channel region including at least one of the NMOS and PMOS device regions; backfilling portions of the recessed regions with a semiconducting silicon alloy to exert a strain on the channel region; forming offset spacers on either side of the gate structures; thinning the polysilicon gate electrodes to a silicidation thickness to allow full metal silicidation through the silicidation thickness; ion implanting the polysilicon gate electrodes to adjust a work function; and, forming a metal silicide through the silicidation thickness to form metal silicide gate electrodes.

摘要翻译： 包括完全硅化栅电极的应变通道NMOS和PMOS器件对及其形成方法，该方法包括提供包含NMOS和PMOS器件区域的半导体衬底，PMOS器件区域包括包括多晶硅栅电极的各自的栅极结构; 在包括所述NMOS和PMOS器件区域中的至少一个的沟道区域的任一侧上形成凹陷区域; 用半导体硅合金回填凹陷区域，以在沟道区域上施加应变; 在栅极结构的任一侧上形成偏置间隔物; 将多晶硅栅电极减薄至硅化厚度，以允许通过硅化物厚度的全金属硅化物; 离子注入多晶硅栅电极以调节功函数; 并通过硅化物厚度形成金属硅化物以形成金属硅化物栅电极。

公开(公告)号：US20060009001A1

公开(公告)日：2006-01-12

申请号：US10864952

申请日：2004-06-10

申请人： Yi-Chun Huang ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Huan-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

发明人： Yi-Chun Huang ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Huan-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/76

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

摘要： Abstract of the Disclosure A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portion reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

摘要翻译： 发明内容已经开发出通过使用相邻和周围的硅 - 锗形状在应变硅层中形成用于MOSFET器件的沟道区的方法。 该方法同时形成导电栅极结构的顶部中的凹部并且在半导体衬底的不被栅极结构占据的部分中，或者位于导电栅极结构的侧面上的虚设间隔物。 选择性限定的凹槽将用于随后容纳硅锗形状，其中硅 - 锗形状位于半导体衬底的凹陷中，从而诱导期望的应变通道区域。 导电栅极结构和半导体衬底部分的凹陷减少了在合金层的外延生长期间跨越侧壁间隔物表面的硅 - 锗桥接的风险，从而降低了栅极到衬底泄漏或短路的风险。

公开(公告)号：US06503848B1

公开(公告)日：2003-01-07

申请号：US09989804

申请日：2001-11-20

申请人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Huan-Just Lin ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Huan-Just Lin ,  Hun-Jan Tao

IPC分类号： H01L21469

CPC分类号： H01L21/32115 ,  H01L21/31055 ,  H01L21/3127 ,  H01L21/32137

摘要： A method is disclosed for smoothing the top surface of a layer of polysilicon which, as deposited, has a rough top surface due to the formation of polysilicon grains. A polymer, such as CxFyBrz, is deposited using chemical vapor deposition. The polymer layer has a thickness large enough so that the top surface of the polymer is at least a critical distance above the peaks of the grains on the top surface of the layer of polysilicon. The layer of polymer and part of the layer of polysilicon are then etched away using an etch back method which etches the polymer and polysilicon at the same etch rate. This results in a layer of polysilicon having a smooth top surface and the same thickness over the entire layer of polysilicon.

摘要翻译： 公开了一种用于平滑多晶硅层的顶表面的方法，由于多晶硅颗粒的形成，沉积的多晶硅层具有粗糙的顶表面。 使用化学气相沉积法沉积聚合物，如CxFyBrz。 聚合物层的厚度足够大，使得聚合物的顶表面至少在多晶硅层顶表面上的晶粒峰值之上的临界距离。 然后使用以相同蚀刻速率蚀刻聚合物和多晶硅的回蚀法蚀刻掉聚合物层和多晶硅层的一部分。 这导致一层多晶硅在整个多晶硅层上具有平滑的顶表面和相同的厚度。

公开(公告)号：US06440875B1

公开(公告)日：2002-08-27

申请号：US09848248

申请日：2001-05-02

申请人： Bor-Wen Chan ,  Mei-Ru Kuo

发明人： Bor-Wen Chan ,  Mei-Ru Kuo

IPC分类号： H01L2131

CPC分类号： H01L29/6659 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/7833

摘要： Within a method for forming a spacer layer, there is first provided a substrate having formed thereover a topographic feature in turn having formed thereover a second microelectronic layer formed of a second material having a second thickness in turn having formed thereover a first microelectronic layer formed of a first material having a first thickness. Within the method, the first material serves as an etch stop for second material and the first thickness is less than the second thickness. The first microelectronic layer and the second microelectronic layer are then successively etched to ultimately form a spacer layer with enhanced dimensional control.

摘要翻译： 在用于形成间隔层的方法中，首先提供了一种在其上形成有地形特征的基底，其上形成有第二微电子层，第二微电子层由具有第二厚度的第二材料形成，第二材料依次形成有第一微电子层， 具有第一厚度的第一材料。 在该方法中，第一材料用作第二材料的蚀刻停止件，第一厚度小于第二厚度。 然后连续地蚀刻第一微电子层和第二微电子层，以最终形成具有增强的尺寸控制的间隔层。

公开(公告)号：US20120196420A1

公开(公告)日：2012-08-02

申请号：US13444715

申请日：2012-04-11

申请人： Tan-Chen Lee ,  Bor-Wen Chan

发明人： Tan-Chen Lee ,  Bor-Wen Chan

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/456 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833 ,  H01L2924/0002

摘要： A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

摘要翻译： 提供了具有改进的滚降电阻率和可靠性的半导体器件。 半导体器件包括覆盖半导体衬底的栅极电介质，覆盖栅极电介质的栅极电极，栅电极上的栅极硅化物区域，与栅极电介质相邻的源极/漏极区域，以及源极/漏极硅化物区域， 漏极区域，其中源极/漏极硅化物区域和栅极硅化物区域具有不同的金属组成。

公开(公告)号：US08173540B2

公开(公告)日：2012-05-08

申请号：US12904809

申请日：2010-10-14

申请人： Tan-Chen Lee ,  Bor-Wen Chan

发明人： Tan-Chen Lee ,  Bor-Wen Chan

IPC分类号： H01L21/4763

CPC分类号： H01L29/456 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833 ,  H01L2924/0002

摘要： A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

摘要翻译： 提供了具有改进的滚降电阻率和可靠性的半导体器件。 半导体器件包括覆盖半导体衬底的栅极电介质，覆盖栅极电介质的栅极电极，栅电极上的栅极硅化物区域，与栅极电介质相邻的源极/漏极区域，以及源极/漏极硅化物区域， 漏极区域，其中源极/漏极硅化物区域和栅极硅化物区域具有不同的金属组成。

公开(公告)号：US20110183508A1

公开(公告)日：2011-07-28

申请号：US12693504

申请日：2010-01-26

申请人： Bor-Wen Chan ,  Fang Wen Tsai

发明人： Bor-Wen Chan ,  Fang Wen Tsai

IPC分类号： H01L21/28

CPC分类号： H01L29/66795 ,  H01L29/66545

摘要： A structure and method for replacement metal gate technology is provided for use in conjunction with semiconductor fins or other devices. An opening is formed in a dielectric by removing a sacrificial gate material such as polysilicon. The surfaces of the semiconductor fin within which a transistor channel is formed, are exposed in the opening. A replacement metal gate is formed by forming a diffusion barrier layer within the opening and over a gate dielectric material, the diffusion barrier layer formation advantageously followed by an in-situ plasma treatment operation. The treatment operation utilizes at least one of argon and hydrogen and cures surface defects in the diffusion barrier layer enabling the diffusion barrier layer to be formed to a lesser thickness. The treatment operation decreases resistivity, densifies and alters the atomic ratio of the diffusion barrier layer, and is followed by metal deposition.

摘要翻译： 提供了用于替代金属栅极技术的结构和方法，用于与半导体鳍片或其它器件结合使用。 通过去除诸如多晶硅的牺牲栅极材料在电介质中形成开口。 在其中形成晶体管沟道的半导体鳍片的表面在开口中露出。 通过在开口内部和栅极电介质材料上形成扩散阻挡层形成替代金属栅极，扩散阻挡层形成有利地进行原位等离子体处理操作。 处理操作利用氩和氢中的至少一种，并固化扩散阻挡层中的表面缺陷，使得扩散阻挡层能够形成较小的厚度。 处理操作降低电阻率，致密化并改变扩散阻挡层的原子比，随后进行金属沉积。