公开(公告)号：US08674490B2

公开(公告)日：2014-03-18

申请号：US13034584

申请日：2011-02-24

申请人： Yong Liu ,  Jiangyuan Zhang ,  Qiuxiao Qian

发明人： Yong Liu ,  Jiangyuan Zhang ,  Qiuxiao Qian

IPC分类号： H01L23/02

CPC分类号： H01L23/49575 ,  H01L23/49524 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.

摘要翻译： 半导体管芯封装。 半导体管芯封装的实施例可用于背光电路。 封装中的系统可以包括桥接电路或其一部分，以及由模制材料或其它封装封装的集成电路管芯，例如驱动器管芯。 桥接电路可以堆叠在引线框架的相对表面上。

公开(公告)号：US20120149149A1

公开(公告)日：2012-06-14

申请号：US13397285

申请日：2012-02-15

申请人： Yong Liu ,  Qiuxiao Qian ,  JiangYuan Zhang ,  Mike Speed ,  Jung Tae Lee ,  Luke Huiyong Chung

发明人： Yong Liu ,  Qiuxiao Qian ,  JiangYuan Zhang ,  Mike Speed ,  Jung Tae Lee ,  Luke Huiyong Chung

IPC分类号： H01L21/56

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.

摘要翻译： 包括100个的模制的无引线封装半导体多芯片模块具有用于全桥电路的四个mosfet 10,12,14,16。 MOSFET可以包括两个N沟道和两个P沟道器件或四个相同类型的MOS器件，但是优选四个N沟道。 在模块100中，存在用于组装mosfet的两个引线框30,40。 特别地，两个N沟道和两个P沟道器件设置在两个引线框之间并封装在电绝缘的模制化合物84中。所得到的封装具有四个上部散热器44.1-44.4，其暴露在模制化合物84中用于转移 从mosfet到周围环境的热量。 不需要引线键。 这可以显着降低RDSON的导通电阻。 顶部或源极 - 漏极引线框架30可以焊接到桥式MOSFET的源极和栅极。

公开(公告)号：US20110140255A1

公开(公告)日：2011-06-16

申请号：US13034584

申请日：2011-02-24

申请人： Yong Liu ,  Jiangyuan Zhang ,  Qiuxiao Qian

发明人： Yong Liu ,  Jiangyuan Zhang ,  Qiuxiao Qian

IPC分类号： H01L23/495 ,  H01L21/50

CPC分类号： H01L23/49575 ,  H01L23/49524 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.

摘要翻译： 半导体管芯封装。 半导体管芯封装的实施例可用于背光电路。 封装中的系统可以包括桥接电路或其一部分，以及由模制材料或其它封装封装的集成电路管芯，例如驱动器管芯。 桥接电路可以堆叠在引线框架的相对表面上。

公开(公告)号：US20100072590A1

公开(公告)日：2010-03-25

申请号：US12235227

申请日：2008-09-22

申请人： Yong Liu ,  Howard Allen ,  Qiuxiao Qian

发明人： Yong Liu ,  Howard Allen ,  Qiuxiao Qian

IPC分类号： H01L21/50 ,  H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49861 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/19105 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Pre-molded component packages that may be as thin as a leadframe for a semiconductor die, systems using the same, and methods of making the same are disclosed. The leads of an exemplary package are exposed at both surfaces at the leadframe. The packages may be stacked upon one another and electrically coupled at the exposed portions of their leads.

摘要翻译： 公开了可以与用于半导体管芯的引线框一样薄的预成型部件封装，使用其的系统及其制造方法。 示例性包装的引线在引线框架的两个表面处露出。 封装可以彼此堆叠并且在引线的暴露部分处电耦合。

公开(公告)号：US20090230518A1

公开(公告)日：2009-09-17

申请号：US12046734

申请日：2008-03-12

申请人： Yong Liu ,  Jiangyuan Zhang ,  Qiuxiao Qian

发明人： Yong Liu ,  Jiangyuan Zhang ,  Qiuxiao Qian

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L23/49575 ,  H01L23/49524 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.

摘要翻译： 半导体管芯封装。 半导体管芯封装的实施例可用于背光电路。 封装中的系统可以包括桥接电路或其一部分，以及由模制材料或其它封装封装的集成电路管芯，例如驱动器管芯。 桥接电路可以堆叠在引线框架的相对表面上。

公开(公告)号：US20090174047A1

公开(公告)日：2009-07-09

申请号：US11971524

申请日：2008-01-09

申请人： Scott Irving ,  Yong Liu ,  Qiuxiao Qian

发明人： Scott Irving ,  Yong Liu ,  Qiuxiao Qian

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49575 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/732 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/05599

摘要： Disclosed are semiconductor die packages having overlapping dice, systems that use such packages, and methods of making such packages. An exemplary die package comprises a leadframe, a first semiconductor die, and a second semiconductor die that has a recessed portion in one of its surfaces. The first die is disposed over a first portion of the leadframe, and the second die is disposed over a second portion of the leadframe with its recess portion overlying at least a portion of the first die. Another exemplary die package comprises a leadframe with a recessed area, a first semiconductor die disposed in the recessed area, and a second semiconductor die overlying at least a portion of the first die. Preferably, electrically conductive regions of both dice are electrically coupled to a conductive region of the leadframe to provide an interconnection between dice that has very low parasitic capacitance and inductance.

摘要翻译： 公开了具有重叠的骰子的半导体管芯封装，使用这种封装的系统以及制造这种封装的方法。 示例性的管芯封装包括引线框架，第一半导体管芯和在其表面之一中具有凹部的第二半导体管芯。 第一管芯设置在引线框架的第一部分上，并且第二管芯设置在引线框架的第二部分上，其凹部覆盖在第一管芯的至少一部分上。 另一示例性管芯封装包括具有凹陷区域的引线框架，设置在凹陷区域中的第一半导体管芯，以及覆盖第一管芯的至少一部分的第二半导体管芯。 优选地，两个骰子的导电区域电耦合到引线框架的导电区域，以提供具有非常低的寄生电容和电感的管芯之间的互连。

公开(公告)号：US08389338B2

公开(公告)日：2013-03-05

申请号：US13276372

申请日：2011-10-19

申请人： Yong Liu ,  Qiuxiao Qian

发明人： Yong Liu ,  Qiuxiao Qian

IPC分类号： H01L21/00

CPC分类号： H01L23/49861 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.

摘要翻译： 多芯片封装在将半导体管芯倒装芯片连接到引线框架之前形成顶部和底部预成型引线框架。 在芯片附接之后，使用底部填充物封装模具的除了一个表面之外的所有其它表面，并且顶部和底部引线框架通过焊料凸块球连接在一起，其中半导体芯片的暴露表面彼此靠近。

公开(公告)号：US08063474B2

公开(公告)日：2011-11-22

申请号：US12026742

申请日：2008-02-06

申请人： Yong Liu ,  Qiuxiao Qian

发明人： Yong Liu ,  Qiuxiao Qian

IPC分类号： H01L23/02

CPC分类号： H01L23/49861 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.

摘要翻译： 多芯片封装在将半导体管芯倒装芯片连接到引线框架之前形成顶部和底部预成型引线框架。 在芯片附接之后，使用底部填充物封装模具的除了一个表面之外的所有其它表面，并且顶部和底部引线框架通过焊料凸块球连接在一起，其中半导体芯片的暴露表面彼此靠近。

公开(公告)号：US08063472B2

公开(公告)日：2011-11-22

申请号：US12020855

申请日：2008-01-28

申请人： Yong Liu ,  William Newberry ,  Margie T. Rios ,  Qiuxiao Qian

发明人： Yong Liu ,  William Newberry ,  Margie T. Rios ,  Qiuxiao Qian

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49562 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： Disclosed in this specification is a buck converter package with stacked dice and a process for forming a buck converter. The package includes a die attach pad with a low side die mounted on one surface and a high side die mounted on the opposing surface. The die attach pad is conductive, such that the drain of the low side die is connected to the source of the high side die through the pad. A controller die controls the gates of the high and low side dies. A plurality of leads extends outside of the package to permit electrical connections to the inside of the package. The high side drain is exposed to one of the surfaces of the package.

摘要翻译： 在本说明书中公开了具有堆叠骰子的降压转换器封装和用于形成降压转换器的工艺。 该封装包括一个安装在一个表面上的具有一个低边裸片的芯片安装板和一个安装在相对表面上的高边模具。 芯片焊盘是导电的，使得低边裸片的漏极通过焊盘连接到高侧裸片的源极。 控制器模具控制高低侧模具的门。 多个引线延伸到封装的外部，以允许电连接到封装的内部。 高侧漏极暴露于封装的一个表面。

公开(公告)号：US07825502B2

公开(公告)日：2010-11-02

申请号：US11971524

申请日：2008-01-09

申请人： Scott Irving ,  Yong Liu ,  Qiuxiao Qian

发明人： Scott Irving ,  Yong Liu ,  Qiuxiao Qian

IPC分类号： H01L23/495 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49575 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/732 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/05599

摘要： Disclosed are semiconductor die packages having overlapping dice, systems that use such packages, and methods of making such packages. An exemplary die package comprises a leadframe, a first semiconductor die, and a second semiconductor die that has a recessed portion in one of its surfaces. The first die is disposed over a first portion of the leadframe, and the second die is disposed over a second portion of the leadframe with its recess portion overlying at least a portion of the first die. Another exemplary die package comprises a leadframe with a recessed area, a first semiconductor die disposed in the recessed area, and a second semiconductor die overlying at least a portion of the first die. Preferably, electrically conductive regions of both dice are electrically coupled to a conductive region of the leadframe to provide an interconnection between dice that has very low parasitic capacitance and inductance.

摘要翻译： 公开了具有重叠的骰子的半导体管芯封装，使用这种封装的系统以及制造这种封装的方法。 示例性的管芯封装包括引线框架，第一半导体管芯和在其表面之一中具有凹部的第二半导体管芯。 第一管芯设置在引线框架的第一部分上，并且第二管芯设置在引线框架的第二部分上，其凹部覆盖在第一管芯的至少一部分上。 另一示例性管芯封装包括具有凹陷区域的引线框架，设置在凹陷区域中的第一半导体管芯，以及覆盖第一管芯的至少一部分的第二半导体管芯。 优选地，两个骰子的导电区域电耦合到引线框架的导电区域，以提供具有非常低的寄生电容和电感的管芯之间的互连。