公开(公告)号：US08933549B2

公开(公告)日：2015-01-13

申请号：US14106654

申请日：2013-12-13

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Kai Liu ,  Lei Shi ,  Jun Lu ,  Anup Bhalla

IPC分类号： H01L23/52 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/24247 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/92246 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

摘要翻译： 双引线框多芯片封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘的第二引线框架; 安装在用作高边MOSFET的第一芯片焊盘上的第一芯片和安装在用作低端MOSFET的第二芯片焊盘上的第二芯片。 封装还可以包括配置为安装在第一裸片焊盘上或与第一芯片集成的第三芯片的旁路容量。 封装还可以包括形成为一体结构的三维连接板作为第二芯片焊盘，用于将第一芯片的顶部接触区域电连接到第二芯片的底部接触区域。 顶部连接板将第二芯片的顶部接触区域和第三芯片的顶部接触区域连接到第一引线框架的外部引脚。

公开(公告)号：US20130147064A1

公开(公告)日：2013-06-13

申请号：US13764336

申请日：2013-02-11

申请人： Renesas Electronics Corporation

发明人： Yukihiro SATO ,  Tomoaki UNO

IPC分类号： H01L23/492

CPC分类号： H01L23/492 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/91 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85439 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/351 ,  H02M7/003 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012

摘要： The reliability of a semiconductor device is improved.A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

摘要翻译： 提高了半导体器件的可靠性。 半导体器件的封装在内部包括形成功率MOSFET的第一半导体芯片和第二半导体芯片以及形成控制第一和第二半导体芯片的控制电路的第三半导体芯片。 第一至第三半导体芯片分别安装在芯片焊盘上。 第一半导体芯片的高侧的源电极接合焊盘通过金属板与管芯焊盘的第一管芯焊盘电连接。 在芯片焊盘7D2的顶面设置有形成在安装有第二半导体芯片的区域中的镀层和形成在金属板接合的区域中的另一个镀层，并且将镀层彼此分离，并且用 在其间不形成镀层的区域。

公开(公告)号：US20130140673A1

公开(公告)日：2013-06-06

申请号：US13487999

申请日：2012-06-04

申请人： Oliver Haeberlen ,  Walter Rieger ,  Martin Vielemeyer ,  Lutz Goergens ,  Martin Poelzl ,  Milko Paolucci ,  Johannes Schoiswohl ,  Joachim Krumrey

发明人： Oliver Haeberlen ,  Walter Rieger ,  Martin Vielemeyer ,  Lutz Goergens ,  Martin Poelzl ,  Milko Paolucci ,  Johannes Schoiswohl ,  Joachim Krumrey

IPC分类号： H01L23/495

CPC分类号： H01L23/495 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L28/40 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/407 ,  H01L29/41 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7809 ,  H01L29/781 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/37099

摘要： A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.

摘要翻译： 公开了半导体器件和方法。 一个实施例提供具有第一n型沟道FET和第二n型沟道FET的半导体管芯。 第一n型沟道FET的源极和第二n型沟道FET的漏极电耦合到第一侧的至少一个接触区域。 第一n型沟道FET的漏极，第一n型沟道FET的栅极，第二n型沟道FET的源极和第二n型沟道FET的栅极电耦合到接触区域 第二面。 第一n型沟道FET和第二n型沟道FET的接触区域彼此电分离。

公开(公告)号：US20130127062A1

公开(公告)日：2013-05-23

申请号：US13741890

申请日：2013-01-15

申请人： Tessera, Inc.

发明人： Belgacem Haba ,  Wael Zohni ,  Richard Dewitt Crisp ,  Ilyas Mohammed ,  Frank Lambrecht

IPC分类号： H01L23/492

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/492 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/09 ,  H01L24/32 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/0912 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/4824 ,  H01L2224/4826 ,  H01L2224/50 ,  H01L2224/73215 ,  H01L2224/73219 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A microelectronic assembly can include a substrate having first and second surfaces each extending in first and second transverse directions, a peripheral edge extending in the second direction, first and second openings extending between the first and second surfaces, and a peripheral region of the second surface extending between the peripheral edge and one of the openings. The assembly can also include a first microelectronic element having a front surface facing the first surface, a rear surface opposite therefrom, and an edge extending between the front and rear surfaces. The assembly can also include a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond the edge of the first microelectronic element. The assembly can also include a plurality of terminals exposed at the second surface, at least one of the terminals being disposed at least partially within the peripheral region.

公开(公告)号：US08395364B2

公开(公告)日：2013-03-12

申请号：US13233669

申请日：2011-09-15

申请人： Yukihiro Sato ,  Tomoaki Uno

发明人： Yukihiro Sato ,  Tomoaki Uno

IPC分类号： H02M1/00

CPC分类号： H01L23/492 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/91 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85439 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/351 ,  H02M7/003 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012

摘要： The reliability of a semiconductor device is improved.A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

摘要翻译： 提高了半导体器件的可靠性。 半导体器件的封装在内部包括形成功率MOS•FET的第一半导体芯片和第二半导体芯片，以及形成控制第一和第二半导体芯片的控制电路的第三半导体芯片。 第一至第三半导体芯片分别安装在芯片焊盘上。 第一半导体芯片的高侧的源电极接合焊盘通过金属板与管芯焊盘的第一管芯焊盘电连接。 在芯片焊盘7D2的顶面设置有形成在安装有第二半导体芯片的区域中的镀层和形成在金属板接合的区域中的另一个镀层，并且将镀层彼此分离，并且用 在其间不形成镀层的区域。

公开(公告)号：US08154129B2

公开(公告)日：2012-04-10

申请号：US12307228

申请日：2008-04-04

申请人： Kikuo Okada ,  Kojiro Kameyama ,  Takahiro Oikawa

发明人： Kikuo Okada ,  Kojiro Kameyama ,  Takahiro Oikawa

IPC分类号： H01L23/492

CPC分类号： H01L23/49562 ,  H01L23/4952 ,  H01L23/49524 ,  H01L24/05 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/7809 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/371 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099

摘要： In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.

摘要翻译： 在功率MOS晶体管中，例如，源极电极形成为与形成在前表面上的多个源极区域共同连接。 因此，电流密度基于源电极的面内电阻而变化，由此提供增加连接源极和引线的导线数量的必要性。 在本发明中，电极结构包括通过电解电镀法形成在焊盘电极10a上的镀铜层10e，以及形成为覆盖铜镀层的上表面和侧表面的镀镍层10f和镀金层 层10e通过化学镀方法。

公开(公告)号：US08125080B2

公开(公告)日：2012-02-28

申请号：US12264823

申请日：2008-11-04

申请人： Keun-hyuk Lee

发明人： Keun-hyuk Lee

IPC分类号： H01L25/16

CPC分类号： H01L24/40 ,  H01L23/3121 ,  H01L24/37 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L25/072 ,  H01L2224/0603 ,  H01L2224/32225 ,  H01L2224/37124 ,  H01L2224/37144 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/144 ,  H05K3/0052 ,  H05K3/284 ,  H05K3/4015 ,  H05K2201/10242 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided are semiconductor power module packages, which are structurally simplified by bonding electrodes onto substrates, and methods of fabricating the same. An exemplary package includes a substrate and semiconductor chips disposed on a top surface of the substrate. Electrodes are bonded to the top surface of the substrate and electrically coupled to the semiconductor chips. Parts of the semiconductor chips are electrically coupled to parts of the electrodes by interconnection lines. An encapsulation unit covers the semiconductor chips, the electrodes, and the interconnection lines and exposes at least top surfaces of the electrodes.

摘要翻译： 提供了通过将电极结合到基板上而被结构简化的半导体功率模块封装及其制造方法。 示例性封装包括设置在基板的顶表面上的基板和半导体芯片。 电极结合到衬底的顶表面并电耦合到半导体芯片。 半导体芯片的一部分通过互连线电耦合到电极的一部分。 封装单元覆盖半导体芯片，电极和互连线，并且至少暴露电极的顶表面。

公开(公告)号：US08124449B2

公开(公告)日：2012-02-28

申请号：US12326529

申请日：2008-12-02

申请人： Georg Meyer-Berg ,  Andreas Schloegl

发明人： Georg Meyer-Berg ,  Andreas Schloegl

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L24/27 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/492 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L25/072 ,  H01L2224/29111 ,  H01L2224/32014 ,  H01L2224/37011 ,  H01L2224/40225 ,  H01L2224/73219 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.

摘要翻译： 一种包括半导体芯片和金属箔的器件。 一个实施例提供了一种包括半导体芯片的器件，该半导体芯片在第一面上具有第一电极，而在第二面上与第一面相反。 第一金属箔以导电方式连接到半导体芯片的第一电极。 第二金属箔以导电的方式连接到半导体芯片的第二电极。

公开(公告)号：US20110241170A1

公开(公告)日：2011-10-06

申请号：US13081642

申请日：2011-04-07

申请人： Oliver Haeberlen ,  Walter Rieger ,  Martin Vielemeyer ,  Lutz Goergens ,  Martin Poelzl ,  Milko Paolucci ,  Johannes Schoiswohl ,  Joachim Krumrey ,  Sonja Krumrey

发明人： Oliver Haeberlen ,  Walter Rieger ,  Martin Vielemeyer ,  Lutz Goergens ,  Martin Poelzl ,  Milko Paolucci ,  Johannes Schoiswohl ,  Joachim Krumrey ,  Sonja Krumrey

IPC分类号： H01L29/92 ,  H01L23/48

CPC分类号： H01L23/495 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L28/40 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0856 ,  H01L29/407 ,  H01L29/41 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7809 ,  H01L29/781 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/37099

摘要： One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.

摘要翻译： 一个方面是单片半导体开关和制造方法。 一个实施例提供具有第一n型沟道FET和第二n型沟道FET的半导体管芯。 第一n型沟道FET的源极和第二n型沟道FET的漏极分别电耦合到半导体管芯的第一侧的至少一个接触区域。 第一n型沟道FET的漏极，第一n型沟道FET的栅极，第二n型沟道FET的源极和第二n型沟道FET的栅极电耦合到接触区域 半导体管芯的与第一侧相对的第二侧。 第一n型沟道FET的漏极，第一n型沟道FET的栅极，第二n型沟道FET的源极和第二n型沟道FET的栅极的接触面积 分别电分离。

公开(公告)号：US20110233746A1

公开(公告)日：2011-09-29

申请号：US12749505

申请日：2010-03-29

申请人： Kai Liu ,  Lei Shi ,  Jun Lu ,  Anup Bhalla

发明人： Kai Liu ,  Lei Shi ,  Jun Lu ,  Anup Bhalla

IPC分类号： H01L23/52 ,  H01L21/60

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/24247 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/92246 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

摘要翻译： 双引线框多芯片封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘的第二引线框架; 安装在用作高边MOSFET的第一芯片焊盘上的第一芯片和安装在用作低端MOSFET的第二芯片焊盘上的第二芯片。 封装还可以包括配置为安装在第一裸片焊盘上或与第一芯片集成的第三芯片的旁路容量。 封装还可以包括形成为一体结构的三维连接板作为第二芯片焊盘，用于将第一芯片的顶部接触区域电连接到第二芯片的底部接触区域。 顶部连接板将第二芯片的顶部接触区域和第三芯片的顶部接触区域连接到第一引线框架的外部引脚。